AFE8220TPZPQ1 datasheet(33/49 Pages) TI1

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Wakeup Interrupt Generator

AFE8220-Q1

www.ti.com....................................................................................................................................................... SBAS455A – JANUARY 2009 – REVISED JULY 2009

Setting a bit of irq0_en allows the generation of an interrupt for the corresponding event. All three IRQ generators

run on the master clock (MCLK). When an interrupt event occurs on a given source signal, a value of 1 is written

to the corresponding bit of irq0_status. This value is held in irq0_status until it is explicitly cleared by writing a 0

to the appropriate bit of irq0_status. A typical sequence upon receipt of an interrupt would be to poll irq0_status

to determine the source of the interrupt, take whatever system action is appropriate, and then clear irq0_status.

Changes to any of the GPIO pins can also be programmed as interrupts. GPIO pin events are defined as

changes from low to high or from high to low, depending on whether the corresponding bit in irq0_gpio_edge is

high or low. GPIO interrupts are enabled by setting the corresponding bit in irq0_gpio_en; they are identified and

cleared by reading and writing the corresponding bit in irq0_gpio_status.

The behavior of the IRQ0 pin is determined by irq0_sense. When irq0_sense is 0, IRQ0 is normally low and goes

high on an unmasked interrupt event. When irq0_sense is 1, IRQ0 is normally high and goes low on an

unmasked interrupt event. Table 21 shows the irq0, irq1, and irq2 operations control settings.

Table 21. IRQ Control Register Settings

PARAMETER

ADDRESS

BITS

irq0_en

15:0

irq1_en

15:0

irq2_en

15:0

irq0_gpio_edge

11:0

irq1_gpio_edge

11:0

irq2_gpio_edge

11:0

irq0_gpio_en

11:0

irq1_gpio_en

11:0

irq2_gpio_en

11:0

irq0_gpio_status

11:0

irq1_gpio_status

11:0

irq2_gpio_status

11:0

irq0_sense

irq1_sense

irq2_sense

irq0_status

15:0

irq1_status

15:0

irq2_status

15:0

The WAKEUP interrupt generator functions in the same way as the IRQ generators with the following exceptions:

1. The WAKEUP generator runs on the RTC clock instead of MCLK;

2. The WAKEUP generator operates when the AFE is in low-power mode, whereas the IRQ generators do not;

and

3. The interrupt sources for the WAKEUP interrupt generator are slightly different.

Table 22 shows the wakeup control settings. Table 23 shows the generator functions.

Table 22. Wakeup Control Register Settings

PARAMETER

ADDRESS

BITS

wakeup_sense

wakeup_gpio_edge

11:0

wakeup_gpio_en

11:0

wakeup_en

15:0

wakeup_status

15:0

wakeup_gpio_status

11:0

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AFE8220TPZPQ1 Datasheet(PDF) 33 Page - Texas Instruments

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