ELECTRICAL CHARACTERISTICS (continued)

LVPECL OUTPUT DRIVER Y[2:0], Y[2:0]

LVPECL INPUT-TO-LVPECL OUTPUT PARAMETERS

JITTER CHARACTERISTICS

CDCP1803-EP

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output frequency, see Figure 3.

0

800

MHz

High-level output voltage

Termination with 50

V

Low-level output voltage

Termination with 50

V

Output voltage swing between Y and Y,

Termination with 50

500

mV

see Figure 3.

5

Output 3-state current

µA

10

Rise and fall times

170

400

ps

Output skew between any LVPECL

See Note A in Figure 7.

15

70

ps

output Y[2:0] and Y[2:0]

Crossing point-to-crossing point

–50

50

ps

distortion

Part-to-part skew

Any Y, see Note B in Figure 7.

50

ps

Output capacitance

1

pF

LOAD

Expected output load

50

Ω

(1)

For an 800-MHz signal, the 50-ps error would result in a duty cycle distortion of ±4% when driven by an ideal clock input signal.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Propagation delay, rising edge

VOX to VOX

320

600

ps

Propagation delay, falling edge

VOX to VOX

320

600

ps

LVPECL pulse skew

VOX to VOX, see Note C in Figure 7.

100

ps

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

JITTER CHARACTERISTICS

12 kHz to 20 MHz,

0.15

divide-by-1 mode

Additive phase jitter from input to

ps rms

LVPECL output Y[2:0], see Figure 2.

50 kHz to 40 MHz,

0.25

divide-by-1 mode

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