8

Preliminary Specifications

4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo

SST30VR041 / SST30VR043

©2001 Silicon Storage Technology, Inc.

S71134-02-000

4/01

381

TABLE

Address Inputs

ROMCS#

(Pin 32)

1. OE# & RAMCS# are pin-shared

WE#

2. X means Don’t Care.

H

H

X

Z

Standby

L

OE# (H)

X

Z

Output Floating

LOE# (L)

X

ROM Read

HRAMCS# (L)

H

RAM Read

H

RAMCS# (L)

L

RAM Write

T8.3 381

TWC

TAW

TCW(2)

TOH

TDH

TDW

TOW

TWR(4)

Data Valid

381 ILL F06.0

Data In

Data Out

WE#

OE#/RAMCS#

High-Z

High-Z (6)

(7)

(8)

Address

TWP(1)

TAS(3)

TWHZ(5)

Notes: 1. A write occurs during the overlap (TWP) of a low RAMCS# and low WE#. A write begins at the latest transition among

RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high,

TWP is measured from the beginning of write to the end of write.

2. TCW is measured from the later of RAMCS# going low to the end of write.

3. TAS is measured from the address valid to the beginning of write.

4. TWR is measured from the end of write to the address change.

5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state.

Inputs of opposite phase of the output must not be applied because bus contention can occur.

6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state.

7. DOUT is the same phase of the latest written data in this write cycle.

8. DOUT is the read data of new address

9. ROMCS# = VIH