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CXD3003 Datasheet(PDF) 130 Page - Sony Corporation |
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CXD3003 Datasheet(HTML) 130 Page - Sony Corporation |
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130 / 137 page  – 130 – CXD3003R Anti Shock fs = 88.2kHz K34 K33 Z–1 Z–1 K31 K16 Z–1 M09 M08 2–7 M0A K35 Comp K12 Anti Shock Reg 2–1 TRK In Reg Note) Set the MSB bit of the K34 coefficient to 0. The comparator input is 1/16 the maximum amplitude of the comparator input. AVRG fs = 88.2kHz M08 AVRG Reg 2–1 VC, TE, FE, RFDC Z–1 2–7 TRK Hold fs = 345Hz K44 K43 Z–1 K42 Z–1 K41 K40 M18 2–7 2–7 M19 K45 TRK Hold Reg SLD In Reg 2–1 K46 THSK (only when TGUP2 is used) THID M0D TRK SERVO FILTER Second-stage output Note) Set the MSB bit of the K42 and K44 coefficients to 0. FCS Hold fs = 345Hz K4C K4B Z–1 K4A Z–1 K49 K48 M10 2–7 2–7 M11 K4D FCS Hold Reg 1 FCS Hold Reg 2 Note) Set the MSB bit of the K4A and K4C coefficients to 0. |
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