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CXD3003 Datasheet(PDF) 44 Page - Sony Corporation

Part # CXD3003
Description  CD Digital Signal Processor with Built-in Digital Servo and DAC
PDF  137 Pages
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Manufacturer  SONY [Sony Corporation]
Direct Link  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXD3003 Datasheet(HTML) 44 Page - Sony Corporation

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– 44 –
CXD3003R
Command
Data 1
Audio CTRL
0
0
Mute
ATT
D23
D22
D21
D20
Data 2
PCT1
PCT2
D19
D18
DADS
SOC2
D17
D16
$AX commands
Command bit
Mute = 0
Mute = 1
Mute off if other mute
conditions are not set.
Mute on. Peak register
reset.
Meaning
Command bit
ATT = 0
ATT = 1
Attenuation off
–12dB
Meaning
Mute conditions
(1) When register A mute = 1.
(2) When Mute pin = 1.
(3) When register 8 D.out Mute F = 1 and the Digital Out is on (MD2 pin = 1).
(4) When GFS stays low for over 35ms (during normal speed).
(5) When register 9 BiliGL MAIN = Sub = 1.
(6) When register A PCT1 = 1 and PCT2 = 0.
(1) to (4) perform zero-cross muting with a 1ms time limit.
Command bit
PCT1
0
0
1
1
PCT2
0
1
0
1
Normal mode
Level meter mode
Peak meter mode
Normal mode
× 0dB
× 0dB
Mute
× 0dB
C1: double; C2: quadruple
C1: double; C2: quadruple
C1: double; C2: double
C1: double; C2: double
Meaning
PCM Gain
ECC error correction ability
Description of level meter mode (see Timing Chart 1-4.)
• When the LSI is set to this mode, it performs digital level meter functions.
• When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO.
The initial 80 bits are Sub Q data (see §2. Subcode Interface). The last 16 bits are LSB first, which are 15-bit
PCM data (absolute values) and an L/R flag.
The L/R flag is high when the 15-bit PCM data is from the left channel and low when the data is from the right
channel.
• The PCM data is reset and the L/R flag is reversed after one readout.
Then maximum value measuring continues until the next readout.



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