CXD3003 datasheet(106/137 Pages) SONY

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CXD3003R

§5-13. COUT Signal

The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by

loading the MIRR signal at both edges of the TZC signal. And the used TZC signal can be selected among

three different phases for each COUT signal application.

• HPTZC: For 1-track jumps

Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a

cut-off 1kHz digital HPF; when MCK = 128Fs.)

• STZC: For COUT signal generation when MIRR is externally input and for applications other than

COUT generation.

This is generated from sampling TE at 700kHz. (when MCK = 128Fs)

• DTZC: For High-speed traverse

Reliable COUT signal generation with a delayed phase STZC signal.

Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance

with the MIRR signal delay during high-speed traverse.

The COUT signal output method is switched with D15 and 14 of $3.

When D15 = 1

: STZC

When D15 = 0 and D14 = 0 : HPTZC

When D15 = 0 and D14 = 1 : DTZC

When the DTZC is selected, the delay can be selected from two values with D14 of $36.

§5-14. Serial Readout Circuit

The following measurement and adjustment results can be read out from the SENS pin by inputting the

readout clock to the SCLK pin by $39. (See Fig. 5-18, Table 5-19 and "Description of SENS Signals".)

Specified commands

$390C: VC AVRG measurement result

$3908: FE AVRG measurement result

$3904: TE AVRG measurement result

$391F: RF AVRG measurement result

$3953: FCS AGCNTL coefficient result

$3963: TRK AGCNTL coefficient result

$391C: TRVSC adjustment result

$391D: FBIAS register value

···

tDLS

tSPW

1/fSCLK

MSB

LSB

XLAT

SCLK

Serial Read Out Data

(SENS)

Item

Symbol

Min.

Typ.

Max.

Unit

SCLK frequency

SCLK pulse width

Delay time

fSCLK

tSPW

tDLS

31.3

MHz

µs

Table 5-19.

During readout, the upper 8 bits of the command register must be 39 (Hex).

Fig. 5-18.

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