STA333W datasheet(27/49 Pages) STMICROELECTRONICS

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STA333W

Doc ID 13365 Rev 2

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Channel input mapping

Each channel received via I2S can be mapped to any internal processing channel via the

channel input mapping registers. This allows for flexibility in processing. The default settings

of these registers map each I2S input channel to its corresponding processing channel.

6.1.3

Configuration register C (addr 0x02)

DDX power output mode

DDX compensation pulse size register

Table 20.

Channel input mapping

Bit

R/W

RST

Name

Description

6R/W

0C1IM

0: processing channel 1 receives left I2S input

1: processing channel 1 receives right I2S input

7R/W

0C2IM

0: processing channel 2 receives left I2S input

1: processing channel 2 receives right I2S input

OCRB

Reserved

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

100

101

Table 21.

DDX power output mode

Bit

R/W

RST

Name

Description

R/W

OM0

The DDX power output mode selects the configuration

of the DDX output:

00: drop compensation

01: discrete output stage: tapered compensation

10: full-power mode

11: variable drop compensation (CSZx bits)

1R/W

1OM1

Table 22.

DDX compensating pulse size

Bit

R/W

RST

Name

Description

R/W

CSZ0

When OM[1:0] = 11, this register determines the size of

the DDX compensating pulse from 0 to 15 clock periods:

0000: 0 ns (0 ticks) compensating pulse size

0001: 20 ns (1 tick) clock period compensating pulse

size

.....

1111: 300 ns (15 ticks) clock period compensating pulse

size

3R/W

0CSZ1

4R/W

1CSZ2

5R/W

0CSZ3

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