L99DZ70XP datasheet(36/47 Pages) STMICROELECTRONICS

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SPI - control and status registers

L99DZ70XP

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Doc ID 15162 Rev 3

5.3

Control register 2

Table 27.

Control register 2 (read/write)

Bit

Name

Comment

OUT1 – OCR

enable

In case of an over-current event the over-current status bit (Status

Recovery Enable bit (OCR) is set, the output will be automatically

reactivated after a delay time resulting in a PWM modulated current with

a programmable duty cycle (bit 5 of control register 3).

Depending on occurrence of over-current event and internal clock phase

it is possible that one recovery cycle is executed even if this bit is set to

zero. The ECV-OCR enable bit is disabled in electrochrome mode

(bit1=1 control register 1).

OUT2 – OCR

enable

OUT3 – OCR

enable

OUT4 – OCR

enable

OUT5 – OCR

enable

OUT6 – OCR

enable

ECV – OCR

enable

Reserved (has to be set to '0')

OUT1 PWM1

enable

If the PWM1/2 Enable bit is set and the output is enabled (control

switched off if PWM1/2 input is low. OUT5, 8 and OUT10 are controlled

by PWM2 input, all other outputs are controlled by PWM1 input.

OUT2 PWM1

enable

OUT3 PWM1

enable

OUT4 PWM1

enable

OUT5 PWM2

enable

OUT6 PWM1

enable

ECV PWM1

enable

0ECV-low voltage

The maximum ECV voltage in electrochrome mode is 1.5V. It

corresponds to the full scale range of the digital to analog converter DAC

set by the bits 7 to 2 of control register 1. If the ECV_low voltage bit is

set to '0', the maximum voltage is limited to 1.2V without changing the

resolution of the DAC. This is the default mode.

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