LPC81XM datasheet(23/67 Pages) NXP

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LPC81xM

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Objective data sheet

Rev. 1.0 — 7 November 2012

23 of 67

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Each oscillator, except the low-frequency oscillator, can be used for more than one

purpose as required in a particular application.

Following reset, the LPC81xM will operate from the IRC until switched by software. This

allows systems to operate without any external crystal and the bootloader code to operate

at a known frequency.

See Figure 9 for an overview of the LPC81xM clock generation.

7.20.1.1

Internal RC Oscillator (IRC)

The IRC may be used as the clock source for the WWDT, and/or as the clock that drives

the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

The IRC can be used as a clock source for the CPU with or without using the PLL. The

IRC frequency can be boosted to a higher frequency, up to the maximum CPU operating

frequency, by the system PLL.

Upon power-up or any chip reset, the LPC81xM use the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.20.1.2

Crystal Oscillator (SysOsc)

The crystal oscillator can be used as the clock source for the CPU, with or without using

the PLL.

The SysOsc operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted

to a higher frequency, up to the maximum CPU operating frequency, by the system PLL.

7.20.1.3

Internal Low-power Oscillator and Watchdog Oscillator (WDOsc)

The nominal frequency of the WDOsc is programmable between 9.4 kHz and 2.3 MHz.

The frequency spread over silicon process variations is

 40%.

The WDOsc is a dedicated oscillator for the windowed WWDT.

The internal low-power 10 kHz (

 40% accuracy) oscillator serves a the clock input to the

WKT. This oscillator can be configured to run in all low power modes.

7.20.2 Clock input

A 3.3 V external clock source (25 MHz typical) can be supplied on the selected CLKIN pin

or a 1.8 V external clock source can be supplied on the XTALIN pin (see Section 13.1).

7.20.3 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The output

divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the

minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.

The PLL is turned off and bypassed following a chip reset and may be enabled by

software. The program must configure and activate the PLL, wait for the PLL to lock, and

then connect to the PLL as a clock source. The PLL settling time is nominally 100

s.

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