LPC81XM datasheet(43/67 Pages) NXP

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LPC81xM

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Objective data sheet

Rev. 1.0 — 7 November 2012

43 of 67

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

11. Dynamic characteristics

11.1 Power-up ramp conditions

<tbd>

11.2 Flash memory

[1]

Number of program/erase cycles.

[2]

Min and max values are valid for Tamb = 40 C to +85 C only.

[3]

Programming times are given for writing <tbd> bytes to the flash. Tamb < +85 C. Data must be written to

the flash in blocks of 256 bytes. Flash programming is accomplished via IAP calls (see LPC800 user

manual). Execution time of IAP calls depends on the system clock and is typically between 1.5 and 2 ms

per 256 bytes.

11.3 External clock for the oscillator in slave mode and CLKIN

Remark: The input voltage on the XTAL1/2 pins must be

 1.95 V (see Table 9). For

connecting the oscillator to the XTAL pins, also see Section 13.1.

[1]

Parameters are valid over operating temperature range unless otherwise specified.

[2]

Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply

voltages.

Table 11.

Flash characteristics

Tamb = 40 C to +85 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as

specified below.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Nendu

endurance

[2][1] 10000

100000

cycles

tret

retention time

powered

[2] 10

years

unpowered

[2] 20

years

ter

erase time

sector or multiple

consecutive

sectors

[2] 95

100

105

tprog

programming

time

[2][3] 0.95

1.05

Table 12.

Dynamic characteristic: external clock (XTALIN or CLKIN inputs)

Tamb = 40 C to +85 C; VDD over specified ranges.[1]

Symbol

Parameter

Conditions

Min

Typ[2]

Max

Unit

fosc

oscillator frequency

MHz

Tcy(clk)

clock cycle time

1000

tCHCX

clock HIGH time

Tcy(clk)  0.4

tCLCX

clock LOW time

Tcy(clk)  0.4

tCLCH

clock rise time

tCHCL

clock fall time

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