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LPC81XM Datasheet(PDF) 30 Page - NXP Semiconductors |
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LPC81XM Datasheet(HTML) 30 Page - NXP Semiconductors |
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30 / 67 page ![]() LPC81xM All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Objective data sheet Rev. 1.0 — 7 November 2012 30 of 67 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller [8] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [9] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. T j T amb P D R th j a – + = Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Tj(max) maximum junction temperature --125 C Table 7. Thermal resistance (TSSOP packages) Symbol Parameter Conditions Thermal resistance in C/W ±15 % TSSOP16 TSSOP20 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in 4 in); still air <tbd> <tbd> Single-layer (4.5 in 3 in); still air <tbd> <tbd> Rth(j-c) thermal resistance from junction to case <tbd> <tbd> Table 8. Thermal resistance value (SO/DIP packages) Symbol Parameter Conditions Thermal resistance in C/W ±15 % SO20 DIP8 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in 4 in); still air <tbd> <tbd> 8-layer (4.5 in 3 in); still air <tbd> <tbd> Rth(j-c) thermal resistance from junction to case <tbd> <tbd> |
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