WM8912 datasheet(81/128 Pages) WOLFSON

81 / 128 page

Production Data

WM8912

PD, Rev 4.0, September 2010

The sequence of signals associated with a single register write operation is illustrated in Figure 46.

Figure 46 Control Interface Register Write

The sequence of signals associated with a single register read operation is illustrated in Figure 47.

SDA

SCLK

device ID

Note: The SDA pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses

R/W

B15

data bits B15 – B8

START

(Write) ACK

ACK

R/W

(Read)

data bits B15 – B8

ACK

STOP

ACK

Rpt

START

Figure 47 Control Interface Register Read

The Control Interface also supports other register operations, as listed above. The interface protocol

for these operations is summarised below. The terminology used in the following figures is detailed in

Table 55.

Note that multiple write and multiple read operations are supported using the auto-increment mode.

This feature enables the host processor to access sequential blocks of the data in the WM8912

TERMINOLOGY

DESCRIPTION

Start Condition

Repeated start

Acknowledge (SDA Low)

¯ ¯

Not Acknowledge (SDA High)

Stop Condition

R/W

¯ ¯

ReadNotWrite

0 = Write

1 = Read

[White field]

Data flow from bus master to WM8912

[Grey field]

Data flow from WM8912 to bus master

Table 55 Control Interface Terminology

Figure 48 Single Register Write to Specified Address

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