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AD1885 Datasheet(PDF) 5 Page - Analog Devices |
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AD1885 Datasheet(HTML) 5 Page - Analog Devices |
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5 / 27 page  –5– REV. 0 AD1885 TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE) Parameter Symbol Min Typ Max Unit RESET Active Low Pulsewidth tRST_LOW 1.0 µs RESET Inactive to BIT_CLK Startup Delay tRST2CLK 162.8 ns SYNC Active High Pulsewidth tSYNC_HIGH 1.3 µs SYNC Low Pulsewidth tSYNC_LOW 19.5 µs SYNC Inactive to BIT_CLK Startup Delay tSYNC2CLK 162.8 ns BIT_CLK Frequency 12.288 MHz BIT_CLK Period tCLK_PERIOD 81.4 ns BIT_CLK Output Jitter * 750 ps BIT_CLK High Pulsewidth tCLK_HIGH 32.56 42 48.84 ns BIT_CLK Low Pulsewidth tCLK_LOW 32.56 38 48.84 ns SYNC Frequency 48.0 kHz SYNC Period tSYNC_PERIOD 20.8 µs Setup to Falling Edge of BIT_CLK tSETUP 5 2.5 ns Hold from Falling Edge of BIT_CLK tHOLD 5ns BIT_CLK Rise Time tRISECLK 2410 ns BIT_CLK Fall Time tFALLCLK 2410 ns SYNC Rise Time tRISESYNC 2410 ns SYNC Fall Time tFALLSYNC 2410 ns SDATA_IN Rise Time tRISEDIN 2410 ns SDATA_IN Fall Time tFALLDIN 2410 ns SDATA_OUT Rise Time tRISEDOUT 2410 ns SDATA_OUT Fall Time tFALLDOUT 2410 ns End of Slot 2 to BIT_CLK, SDATA_IN Low tS2_PDOWN 010 ms Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) tSETUP2RST 15 ns Rising Edge of RESET to HI-Z Delay tOFF 25 ns Propagation Delay 15 ns RESET Rise Time 50 ns Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid 15 ns NOTES *Output jitter is directly dependent on crystal input jitter. Specifications subject to change without notice. |
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