Voutmin = Ontimemin • Fsmax Vinmax + Ioutmin(Rds,ls - Rds,hs) - Ioutmin(RL + Rds,ls)

(

)

TPS56921

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SLVSBL4 – OCTOBER 2012

The minimum output voltage and maximum output voltage can be limited by the minimum on time of the high-

side MOSFET and bootstrap voltage (BOOT-PH voltage) respectively. More discussions are located in Minimum

On Time and Maximum Switching Frequency Limitations and Bootstrap Voltage (BOOT) and Low Dropout

Operation.

Minimum On Time and Maximum Switching Frequency Limitations

The current-mode architecture of the device requires a settling time before accurate current measurements can

occur, therefore a minimum on-time spec exists. The output voltage may be limited by the minimum controllable

on time depending on the input voltage, load current and switching frequency, and so on. The minimum output

voltage is given by Equation 2.

(2)

Where:

Voutmin = minimum achievable output voltage

Ontimemin = minimum controllable on-time (150 nsec maximum @ 2A load current)

Fsmax = maximum switching frequency including tolerance

Vinmax = maximum input voltage

Ioutmin = minimum load current

Rds,hs = high side MOSFET on resistance (26 m

Ω typical)

Rds,ls = low side MOSFET on resistance (19 m

Ω typical)

RL = series resistance of output inductor

If the minimum on-time limitation is exceeded, the device may begin pulse-skipping. In this case, the device will

act as if the operational switching frequency has dropped, but in reality it may probably only skip a few cycles.

Though this will increase the output ripple, the output of the converter will remain in regulation. It is up to the user

to determine whether to choose a switching frequency that keeps the operation away from the pulse-skipping

regime of operation or to run at a reduced input voltage to keep the operation away from pulse-skipping mode or

to run a higher frequency that may pulse-skip if the duty ratio becomes too low.

Safe Start-up into Pre-Biased Outputs

The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During

monotonic pre-biased startup, the low-side MOSFET is not allowed to sink current until the SS pin voltage is

higher than 1.4V.

Error Amplifier

The device uses a transconductance error amplifier. The error amplifier compares the VSENSE pin voltage to the

lower of the SS pin voltage or the internal 0.8V voltage reference. The transconductance of the error amplifier is

1300

μA/V during normal operation. The frequency compensation network is connected between the COMP pin

and ground.

Slope Compensation

The device adds a compensating ramp to the switch current signal. This slope compensation prevents sub-

harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.

Enable and Adjusting Under-Voltage Lockout (EN and UVLO)

The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold

voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator

stops switching and enters low Iq state.

Copyright © 2012, Texas Instruments Incorporated

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