TPS56921

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SLVSBL4 – OCTOBER 2012

Any code >76 is illegal except for the following special control codes:

Table 4. Special Control Codes

Special Code

Function

1111000

Set delay from PWRGD fault to PWRGD pin pulldown to zero

1111001

Set delay from PWRGD fault to PWRGD pin pulldown to 4 CLK cycles (default)

1111010

Set delay from PWRGD fault to PWRGD pin pulldown to 8 CLK cycles

1111011

Set delay from PWRGD fault to PWRGD pin pulldown to 4 CLK cycles (default)

1111111

Change back to external regulation mode

Explanation of Special Codes - PWRGD Blanking Control Codes

compared to the UV/OV thresholds. If this happens, it will cause the PWRGD signal to temporarily indicate a fault

condition.

If this is not the desired behavior, it is possible to “blank” the PWRGD being pulled down for some number of

CLK cycles, whether the CLK frequency is being set by an RT resistor or by an external CLK at the RT/CLK pin.

The user can set this delay to 4, 8 or 16 CLK cycles using the 11110xx codes shown on the previous page. On

power-up, the delay defaults to 4 clock cycles. The user can reset the blanking time using these codes at any

time without affecting any other device behavior.

Alternatively, the user can avoid this by sequentially programming the VOUT in smaller steps. This method

allows the system enough time to respond to large VOUT transitions. The same behavior can occur when

changing from external to internal mode, so the user should first select a VOUT equal to the externally-set

VOUT, then move in small steps to the desired VOUT.

Explanation of Special Codes – Return to External Control Mode

It may be desired to return the IC to being controlled by the external resistor divider feeding back to the VSENSE

TPS56921 will switch back to external feedback mode. The next write of a valid VOUT code to the serial

interface will return the part to internal regulation mode.

None of the other special codes change the VOUT voltage, nor will they cause a switch from External to Internal

regulation modes. Note that code 1111000 puts the part into no-delay mode if it is desired that PWRGD indicates

that the output is temporarily out of regulation.

ChkSum Bit

The ChkSum bit should be set by the Master controller to be the exclusive-OR of the D[6:0] bits (even parity).

This will be used by the TPS56921 to check that a valid data byte was received. If ChkSum is not equal to the

exclusive-OR of the D[6:0] bits, the TPS56921 assumes that an error occurred during the data transmission, and

it will not send an ACK bit, nor will it reset the VOUT to the received code. The Master should try again to send

the data.

Unless they are among the previously-discussed “Special Codes”, sending D[6:0] bits outside of the range 0 to

76 decimal causes the TPS56921 to assume that an error occurred during the data transmission, and it will not

send an ACK bit, nor will it change the VOUT. The Master should try again to send the data.

Small Signal Model for Loop Response

Figure 21 shows an equivalent model for the device control loop which can be modeled in a circuit simulation

program to check frequency response and transient responses. The error amplifier is a transconductance

amplifier with a gm of 1300

μA/V. The error amplifier can be modeled using an ideal voltage controlled current

source. The resistor Roea (2.38 M

Ω) and capacitor Coea (20.7 pF) model the open loop gain and frequency

response of the error amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the

control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of

the power stage and frequency compensation respectively. Plotting a/b shows the small signal response of the

appropriate load step amplitude and step rate in a time domain analysis.

Copyright © 2012, Texas Instruments Incorporated

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