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WM8737CLGEFL/R Datasheet(PDF) 7 Page - Wolfson Microelectronics plc |
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WM8737CLGEFL/R Datasheet(HTML) 7 Page - Wolfson Microelectronics plc |
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7 / 40 page ![]() Production Data WM8737L w PD, Rev 4.4, January 2012 7 Test Conditions DCVDD = 1.5V, AVDD = MVDD = 3.3V, TA = +25 oC, 1kHz -1dBFS signal, Normal Power Mode, fs = 48kHz, PGA gain = 0dB, 24- bit audio data, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Line Inputs (LINPUT1/2/3, RINPUT1/2/3) to ADC – MIC pre-amp BYPASSED Full Scale Input Signal Level (for ADC 0dB Input at 0dB Gain) AVDD = 3.3V 1.0 V rms AVDD = 1.8V 0.545 Signal to Noise Ratio (A-weighted) (Note 1) SNR AVDD = 3.3V, Normal Power Mode 90 97 dB AVDD = 2.7V, Normal Power Mode 95 AVDD = 1.8V, Normal Power Mode 92 AVDD = 3.3V, Low Power Mode 95 AVDD = 2.7V, Low Power Mode 93 AVDD = 1.8V, Low Power Mode 90 Dynamic Range (A-weighted) (Note 2) DNR -60dBFS, Normal Power Mode 90 97 dB -60dBFS, Low Power Mode 95 Total Harmonic Distortion (Note 3) THD -1dB input -84 (0.006%) dB % -1dB input, AVDD=1.8V -81 (0.009%) ADC Channel Separation (Note 4) 1kHz signal 105 dB Channel Matching 1kHz signal 0.2 dB Programmable Gain Amplifier (PGA) Programmable Gain -97 0 30 dB Programmable Gain Step Size Monotonic 0.5 dB Gain Error (Deviation from ideal 0.5dB/step gain characteristic) 1kHz signal -0.3 0.3 dB Input Resistance 0dB gain 30 k 30dB gain 1.9 Input Capacitance 16.9pF pF Automatic Level Control (ALC) Typical Record Level -18 -3 dB Gain Hold Time (Note 5) tHLD MCLK = 12.288MHz (Note 3) 0, 2.67, 5.33, 10.67, … , 43691 (time doubles with each step) ms Gain Ramp-Up (Decay) Time (Notes 6, 7) tDCY 33.6, 67.2, 134.4, … , 3441 (time doubles with each step) ms Gain Ramp-Down (Attack) Time (Notes 6, 7) tATK 8.4, 16.8, 33.6, … , 8600 (time doubles with each step) ms |
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