WM8737CLGEFLSLASHR datasheet(28/40 Pages) WOLFSON

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WM8737L

Production Data

PD, Rev 4.4, January 2012

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

LRP

Right, left & I2S modes – ADCLRC

polarity

1 = invert ADCLRC polarity

0 = normal ADCLRC polarity

DSP Mode – mode A/B select

1 = MSB is available on 1st BCLK

rising edge after ADCLRC rising edge

(mode B)

0 = MSB is available on 2nd BCLK

rising edge after ADCLRC rising edge

(mode A)

Master / Slave Mode Control

1: Master Mode

0: Slave Mode

SDODIS

ADCDAT serial data pin disable

0: ADCDAT pin enabled

1: ADCDAT pin off (high impedance)

Table 14 Audio Data Format Control

Note: Right Justified mode does not support 32-bit data. If WL=11 in Right justified mode, the actual

word length is 24 bits.

To prevent any communication problems on the Audio Interface, the interface is disabled (ADCDAT

tristated and floating) when the WM8737L starts up. Once the Audio Interface and sample rates have

been programmed, the audio interface can be activated under software control by setting the AI bit

(see “Power Management” section).

MASTER CLOCK AND AUDIO SAMPLE RATES

The master clock (MCLK) is used to operate the digital filters and the noise shaping circuits. The

WM8737L supports a wide range of master clock frequencies, and can generate many commonly

used audio sample rates directly from the master clock.

There are two clocking modes:



‘Normal’ mode supports master clocks of 128fs, 192fs, 256fs, 384fs, and their multiples



USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in

systems with a USB interface, and eliminates the need for an external PLL to generate

another clock frequency for the audio ADC.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8 (08h)

Clocking and

Sample Rate

Control

CLKDIV2

Master Clock Divide by 2

1: MCLK is divided by 2

0: MCLK is not divided

USB

Clocking Mode Select

1: USB Mode

0: ‘Normal’ Mode

5:1

SR[4:0]

0000

Sample Rate Control

AUTO

DETECT

Clock Ratio Autodetect

(Slave Mode Only)

0: Autodetect Off

1: Autodetect On

Table 15 Clocking and Sample Rate Control

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