MCP47DA1 datasheet(37/76 Pages) MICROCHIP

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DS25118D-page 37

MCP47DA1

5.3

Serial Commands

The

MCP47DA1

devices

support

two

serial

commands. These commands are:

• Write Operation

• Read Operation

The I2C command formats have been defined to

support the SMBus version 2.0 Write Byte/Word

Protocol formats and Read Byte/Word Protocol

formats. The SMBus specification that defines this

operation is Section 5 of the Version 2.0 document

(August 3, 2000).

This protocol format may be convenient for customers

using library routines for the I2C bus, where all they

need to do is specify the command (Read, Write, ...)

with the device address, the register address, and the

data.

5.3.1

WRITE OPERATION

The write operation requires the Start condition, control

byte, acknowledge, command code, acknowledge,

data byte, acknowledge and Stop (or Restart) condi-

tion. The control (slave address) byte requires the R/W

bit equal to a logic zero (R/W = 0) to generate a write

sequence. The MCP47DA1 is responsible for generat-

ing the Acknowledge (A) bits.

Data is written to the MCP47DA1 after every byte

transfer (during the A bit). If a Stop or Restart condition

is generated during a data transfer (before the A bit),

the data will not be written to MCP47DA1.

Data bytes may be written after each Acknowledge.

The command is terminated once a Stop (P) condition

occurs. Refer to Figure 5-11 for the single byte write

sequence and Figure 5-12 for the generic (multi-byte)

write sequence. For a single byte write, the master

sends a Stop or Restart condition after the first data

byte is sent.

The MSb of each data byte is a “Don’t Care”, since the

wiper register is only 7-bits wide.

The command is terminated once a Stop (P) or Restart

(S) condition occurs.

Figure 5-13 shows the I2C write communication

behavior of the master device and the MCP47DA1

device and the resultant I2C bus values.

5.3.2

READ OPERATION

The read operation requires the Start condition, control

byte, acknowledge, command code, acknowledge,

Restart condition, control byte, acknowledge, data

byte, the master generating the A and Stop (or Restart)

condition. The first control byte requires the R/W bit

equal to a logic zero (R/W = 0) to write the command

code, while the second control byte requires the R/W

bit equal to a logic one (R/W = 1) to generate a read

sequence. The MCP47DA1 will A the slave address

byte and A all the data bytes. The I2C master will A the

slave address byte and the last data byte. If there are

multiple data bytes, the I2C master will A all data bytes

except the last data byte (which it will A).

The MCP47DA1 maintains control of the SDA signal

until all data bits have been clocked out.

The command is terminated once a Stop (P) or Restart

(S) condition occurs. Refer to Figure 5-14 for the read

command sequence. For a single read, the master

sends a Stop or Restart condition after the first data

byte (and A bit) is sent from the slave.

The MSb of each data byte is always a ‘0’, since the

wiper register is only 7-bits wide.

Figure 5-15 shows the I2C read communication

behavior of the master device and the MCP47DA1

device and the resultant I2C bus values.

Note:

A command code with a non-zero value

will cause the data not to be written to the

wiper register

Note:

A command code with a non-zero value

will cause the data not to be read from the

wiper register

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