MCP47DA1 datasheet(45/76 Pages) MICROCHIP

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 2012-2013 Microchip Technology Inc.

DS25118D-page 45

MCP47DA1

7.0

OUTPUT BUFFER

As the device powers up, the VOUT pin will float to an

unknown value. When the device’s VDD is above the

transistor threshold voltage of the device, the output

will start being pulled low. After the VDD is above the

POR/BOR trip point (VBOR/VPOR), the resistor net-

work’s wiper will be loaded with the POR value (40h,

which is mid-scale). The input voltage to the buffer will

be the VREF/2. The output voltage of the buffer (VOUT)

may not be within specification until the device VDD is

at the minimum operating voltage (2.7V). The outputs’

slew rate and settling time must also be taken into

account.

7.1

Output Buffer/VOUT Operation

The DAC output is buffered with a low power and

precision output amplifier (op amp). This amplifier

provides a rail-to-rail output with low offset voltage and

low noise. The amplifier’s output can drive the resistive

and capacitive loads without oscillation. The amplifier

provides a maximum load current which is enough for

most programmable voltage reference applications.

Figure 7-1 shows a block diagram.

FIGURE 7-1:

Output Buffer Block

Diagram.

7.1.1

OUTPUT VOLTAGE

The volatile DAC register’s value controls the analog

VOUT voltage. The volatile wiper register’s value is

unsigned binary. The formula for the output voltage is

given in Equation 7-1.

EQUATION 7-1:

CALCULATING OUTPUT

VOLTAGE (VOUT)

The serial shift register’s value will be latched on the

falling edge of the acknowledge pulse of the Write

command’s last byte. Then the VOUT voltage will start

driving to the new value.

The following events update the analog voltage output

(VOUT):

• Power-On-Reset.

• Falling edge of the acknowledge pulse of the last

Write command byte.

7.1.2

STEP VOLTAGE (VS)

The Step voltage is dependent on the device resolution

(64 RS) and the output voltage range (VZS to VFS).

Equation 7-2 shows the calculation for the step resis-

tance.

EQUATION 7-2:

VS CALCULATION

Table 7-1 shows the calculated VOUT voltages for the

given volatile wiper register value. These calculations

are based on different VREF voltage values (1.5V, 3.3V,

and 5.0V) with an assumption that RFS = RZS = 0.

Note 1: The load resistance must stay higher

than 5 k

 for the stable and expected

analog

output

(to

meet

electrical

specifications). Refer to:

•

Section 1.0 “Electrical Charac-

teristics” for the specifications of

the output amplifier.

•

Section 7.3 “Driving Resistive

and Capacitive Loads” for addi-

tional design information.

2: The output amplifier’s input is not rail-to-

rail, and requires a 1.0V delta to the VDD

voltage to ensure output linearity.

This is not an issue for most voltages,

since the maximum voltage on the ampli-

fier input is the Full-Scale voltage (VFS).

VFS = 2/3 * VREF. But when the VDD (=

VREF) voltage is lower than 3.0V, the

delta voltage is less than 1.0V and the

amplifier will not be in the linear region for

the codes near the full-scale value.

For device VDD voltages  3.0V, the VREF

pin can be tied to VDD. For VDD voltages

< 3.0V, the maximum VREF voltage is:

(VDD - 1.0V) / (2/3)

VOUT

Amp

Gain =1x

N = wiper code = 0 to 64;

VOUT = VZS + (N * VS)

VZS is the VOUT voltage when the wiper code = 00h.

VZS =

VREF

When RFS = RZS = 0 :

VS =

(VFS - VZS)

VFS is the VOUT voltage when the wiper code is at

full scale (SSR = 60h through 7Fh).

VZS is the VOUT voltage when the wiper code is at

zero scale (SSR = 00h through 20h).

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