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LCMXO2-640ZE-2TG100C Datasheet(PDF) 62 Page - Lattice Semiconductor |
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LCMXO2-640ZE-2TG100C Datasheet(HTML) 62 Page - Lattice Semiconductor |
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62 / 106 page  3-23 DC and Switching Characteristics MachXO2 Family Data Sheet MachXO2 External Switching Characteristics – ZE Devices 1, 2, 3, 4, 5, 6, 7 Over Recommended Operating Conditions Parameter Description Device -3 -2 -1 Units Min. Max. Min. Max. Min. Max. Clocks Primary Clocks fMAX_PRI 8 Frequency for Primary Clock Tree All MachXO2 devices — 150 — 125 — 104 MHz tW_PRI Clock Pulse Width for Primary Clock All MachXO2 devices 1.00 — 1.20 — 1.40 — ns tSKEW_PRI Primary Clock Skew Within a Device MachXO2-256ZE — 1250 — 1272 — 1296 ps MachXO2-640ZE — 1161 — 1183 — 1206 ps MachXO2-1200ZE — 1213 — 1267 — 1322 ps MachXO2-2000ZE — 1204 — 1250 — 1296 ps MachXO2-4000ZE — 1195 — 1233 — 1269 ps MachXO2-7000ZE — 1243 — 1268 — 1296 ps Edge Clock fMAX_EDGE 8 Frequency for Edge Clock MachXO2-1200 and larger devices —210 —175 —146 MHz Pin-LUT-Pin Propagation Delay tPD Best case propagation delay through one LUT-4 All MachXO2 devices — 9.35 — 9.78 — 10.21 ns General I/O Pin Parameters (Using Primary Clock without PLL) tCO Clock to Output - PIO Output Register MachXO2-256ZE — 10.46 — 10.86 — 11.25 ns MachXO2-640ZE — 10.52 — 10.92 — 11.32 ns MachXO2-1200ZE — 11.24 — 11.68 — 12.12 ns MachXO2-2000ZE — 11.27 — 11.71 — 12.16 ns MachXO2-4000ZE — 11.28 — 11.78 — 12.28 ns MachXO2-7000ZE — 11.22 — 11.76 — 12.30 ns tSU Clock to Data Setup - PIO Input Register MachXO2-256ZE -0.21 — -0.21 — -0.21 — ns MachXO2-640ZE -0.22 — -0.22 — -0.22 — ns MachXO2-1200ZE -0.25 — -0.25 — -0.25 — ns MachXO2-2000ZE -0.27 — -0.27 — -0.27 — ns MachXO2-4000ZE -0.31 — -0.31 — -0.31 — ns MachXO2-7000ZE -0.33 — -0.33 — -0.33 — ns tH Clock to Data Hold - PIO Input Register MachXO2-256ZE 3.96 — 4.25 — 4.65 — ns MachXO2-640ZE 4.01 — 4.31 — 4.71 — ns MachXO2-1200ZE 3.95 — 4.29 — 4.73 — ns MachXO2-2000ZE 3.94 — 4.29 — 4.74 — ns MachXO2-4000ZE 3.96 — 4.36 — 4.87 — ns MachXO2-7000ZE 3.93 — 4.37 — 4.91 — ns |
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