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LCMXO2-640ZE-2TG100C Datasheet(PDF) 64 Page - Lattice Semiconductor |
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LCMXO2-640ZE-2TG100C Datasheet(HTML) 64 Page - Lattice Semiconductor |
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64 / 106 page  3-25 DC and Switching Characteristics MachXO2 Family Data Sheet tHPLL Clock to Data Hold - PIO Input Register MachXO2-1200ZE 0.66 — 0.68 — 0.80 — ns MachXO2-2000ZE 0.68 — 0.70 — 0.83 — ns MachXO2-4000ZE 0.68 — 0.71 — 0.84 — ns MachXO2-7000ZE 0.73 — 0.74 — 0.87 — ns tSU_DELPLL Clock to Data Setup - PIO Input Register with Data Input Delay MachXO2-1200ZE 5.14 — 5.69 — 6.20 — ns MachXO2-2000ZE 5.11 — 5.67 — 6.17 — ns MachXO2-4000ZE 5.27 — 5.84 — 6.35 — ns MachXO2-7000ZE 5.15 — 5.71 — 6.23 — ns tH_DELPLL Clock to Data Hold - PIO Input Register with Input Data Delay MachXO2-1200ZE -1.36 — -1.36 — -1.36 — ns MachXO2-2000ZE -1.35 — -1.35 — -1.35 — ns MachXO2-4000ZE -1.43 — -1.43 — -1.43 — ns MachXO2-7000ZE -1.41 — -1.41 — -1.41 — ns Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Aligned 9 tDVA Input Data Valid After CLK All MachXO2 devices, all sides — 0.382 — 0.401 — 0.417 UI tDVE Input Data Hold After CLK 0.670 — 0.684 — 0.693 — UI fDATA DDRX1 Input Data Speed — 140 — 116 — 98 Mbps fDDRX1 DDRX1 SCLK Frequency — 70 — 58 — 49 MHz Generic DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Centered 9 tSU Input Data Setup Before CLK All MachXO2 devices, all sides 1.319 — 1.412 — 1.462 — ns tHO Input Data Hold After CLK 0.717 — 1.010 — 1.340 — ns fDATA DDRX1 Input Data Speed — 140 — 116 — 98 Mbps fDDRX1 DDRX1 SCLK Frequency — 70 — 58 — 49 MHz Generic DDRX2 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Aligned 9 tDVA Input Data Valid After CLK MachXO2-640U, MachXO2-1200/U and larger devices, bottom side only — 0.361 — 0.346 — 0.334 UI tDVE Input Data Hold After CLK 0.602 — 0.625 — 0.648 — UI fDATA DDRX2 Serial Input Data Speed —280 —234 —194 Mbps fDDRX2 DDRX2 ECLK Frequency — 140 — 117 — 97 MHz fSCLK SCLK Frequency — 70 — 59 — 49 MHz Generic DDRX2 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Centered 9 tSU Input Data Setup Before CLK MachXO2-640U, MachXO2-1200/U and larger devices, bottom side only 0.472 — 0.672 — 0.865 — ns tHO Input Data Hold After CLK 0.363 — 0.501 — 0.743 — ns fDATA DDRX2 Serial Input Data Speed —280 —234 —194 Mbps fDDRX2 DDRX2 ECLK Frequency — 140 — 117 — 97 MHz fSCLK SCLK Frequency — 70 — 59 — 49 MHz Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input - GDDRX4_RX.ECLK.Aligned 9 tDVA Input Data Valid After ECLK MachXO2-640U, MachXO2-1200/U and larger devices, bottom side only — 0.307 — 0.316 — 0.326 UI tDVE Input Data Hold After ECLK 0.662 — 0.650 — 0.649 — UI fDATA DDRX4 Serial Input Data Speed —420 —352 —292 Mbps fDDRX4 DDRX4 ECLK Frequency — 210 — 176 — 146 MHz fSCLK SCLK Frequency — 53 — 44 — 37 MHz Parameter Description Device -3 -2 -1 Units Min. Max. Min. Max. Min. Max. |
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