PIC24F32KA302-ISLASHML datasheet(113/364 Pages) MICROCHIP

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DS39995D-page 113

PIC24FV32KA304 FAMILY

8.4

Interrupt Setup Procedures

8.4.1

INITIALIZATION

To configure an interrupt source:

Set the NSTDIS control bit (INTCON1<15>) if

nested interrupts are not desired.

Select the user-assigned priority level for the

interrupt source by writing the control bits in the

appropriate IPCx register. The priority level will

depend on the specific application and type of

interrupt source. If multiple priority levels are not

desired, the IPCx register control bits for all

enabled interrupt sources may be programmed

to the same non-zero value.

Clear the interrupt flag status bit associated with

the peripheral in the associated IFSx register.

Enable the interrupt source by setting the

interrupt enable control bit associated with the

source in the appropriate IECx register.

8.4.2

INTERRUPT SERVICE ROUTINE

The method that is used to declare an ISR (Interrupt

Service Routine) and initialize the IVT with the correct

vector address depends on the programming language

(i.e., C or assembly) and the language development

toolsuite that is used to develop the application. In

general, the user must clear the interrupt flag in the

appropriate IFSx register for the source of the interrupt

that the ISR handles. Otherwise, the ISR will be

re-entered immediately after exiting the routine. If the

ISR is coded in assembly language, it must be termi-

nated using a RETFIE instruction to unstack the saved

PC value, SRL value and old CPU priority level.

8.4.3

TRAP SERVICE ROUTINE (TSR)

A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the

INTCON1 register must be cleared to avoid re-entry

into the TSR.

8.4.4

INTERRUPT DISABLE

All user interrupts can be disabled using the following

procedure:

Push the current SR value onto the software

stack using the PUSH instruction.

Force the CPU to Priority Level 7 by inclusive

ORing the value, OEh with SRL.

To enable user interrupts, the POP instruction may be

used to restore the previous SR value.

Only user interrupts with a priority level of 7 or less can

be disabled. Trap sources (Level 8-15) cannot be

disabled.

The DISI instruction provides a convenient way to

disable interrupts of Priority Levels 1-6 for a fixed

period. Level 7 interrupt sources are not disabled by

the DISI instruction.

Note:

At a device Reset, the IPCx registers are

initialized, such that all user interrupt

sources are assigned to Priority Level 4.

PIC24F32KA302-I/ML Datasheet(PDF) 113 Page - Microchip Technology

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