PIC24F32KA302-ISLASHML datasheet(147/364 Pages) MICROCHIP

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DS39995D-page 147

PIC24FV32KA304 FAMILY

14.0 INPUT CAPTURE WITH

DEDICATED TIMERS

All devices in the PIC24FV32KA304 family feature

three independent input capture modules. Each of the

modules offers a wide range of configuration and

operating options for capturing external pulse events,

and generating interrupts.

Key features of the input capture module include:

• Hardware-configurable for 32-bit operation in all

modes by cascading two adjacent modules

• Synchronous and Trigger modes of output

compare operation, with up to 20 user-selectable

Sync/trigger sources available

• A 4-level FIFO buffer for capturing and holding

timer values for several events

• Configurable interrupt generation

• Up to 6 clock sources available for each module,

driving a separate internal 16-bit counter

The module is controlled through two registers: ICxCON1

(Register 14-1) and ICxCON2 (Register 14-2). A general

block diagram of the module is shown in Figure 14-1.

14.1

General Operating Modes

14.1.1

SYNCHRONOUS AND TRIGGER

MODES

By default, the input capture module operates in a

Free-Running mode. The internal 16-bit counter,

ICxTMR, counts up continuously, wrapping around

from FFFFh to 0000h on each overflow, with its period

synchronized to the selected external clock source.

When a capture event occurs, the current 16-bit value

of the internal counter is written to the FIFO buffer.

In Synchronous mode, the module begins capturing

events on the ICx pin as soon as its selected clock

source is enabled. Whenever an event occurs on the

selected Sync source, the internal counter is reset. In

Trigger mode, the module waits for a Sync event from

another internal module to occur before allowing the

internal counter to run.

Standard, free-running operation is selected by setting

the SYNCSELx bits to ‘00000’ and clearing the ICTRIG

bit (ICxCON2<7>). Synchronous and Trigger modes

are selected any time the SYNCSELx bits are set to

any value except ‘00000’. The ICTRIG bit selects

either Synchronous or Trigger mode; setting the bit

selects Trigger mode operation. In both modes, the

SYNCSELx bits determine the Sync/trigger source.

When the SYNCSELx bits are set to ‘00000’ and

ICTRIG is set, the module operates in Software Trigger

mode. In this case, capture operations are started by

manually setting the TRIGSTAT bit (ICxCON2<6>).

FIGURE 14-1:

INPUT CAPTURE x BLOCK DIAGRAM

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is

not intended to be a comprehensive

reference source. For more information,

refer to the “PIC24F Family Reference

Manual”, Section 34. “Input Capture

with Dedicated Timer” (DS39722).

ICxBUF

4-Level FIFO Buffer

ICx Pin

ICM<2:0>

Set ICxIF

Edge Detect Logic

ICI<1:0>

ICOV, ICBNE

Interrupt

Logic

System Bus

Prescaler

Counter

1:1/4/16

and

Clock Synchronizer

Event and

Trigger and

Sync Logic

Clock

Select

IC Clock

Sources

Trigger and

Sync Sources

ICTSEL<2:0>

SYNCSEL<4:0>

Trigger

ICxTMR

Increment

Reset

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