PIC24F32KA302-ISLASHML datasheet(151/364 Pages) MICROCHIP

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DS39995D-page 151

PIC24FV32KA304 FAMILY

15.0 OUTPUT COMPARE WITH

DEDICATED TIMERS

All devices in the PIC24FV32KA304 family feature

3 independent output compare modules. Each of these

modules offers a wide range of configuration and

operating options for generating pulse trains on internal

device events. Also, the modules can produce

Pulse-Width Modulated (PWM) waveforms for driving

power applications.

Key features of the output compare module include:

• Hardware-configurable for 32-bit operation in all

modes by cascading two adjacent modules

• Synchronous and Trigger modes of output

compare operation, with up to 21 user-selectable

Sync/trigger sources available

• Two separate Period registers (a main register,

OCxR, and a secondary register, OCxRS) for

greater flexibility in generating pulses of varying

widths

• Configurable for single pulse or continuous pulse

generation on an output event, or continuous

PWM waveform generation

• Up to 6 clock sources available for each module,

driving a separate internal 16-bit counter

15.1

General Operating Modes

15.1.1

SYNCHRONOUS AND TRIGGER

MODES

By default, the output compare module operates in a

Free-Running mode. The internal 16-bit counter,

OCxTMR, counts up continuously, wrapping around

from FFFFh to 0000h on each overflow, with its period

synchronized to the selected external clock source.

Compare or PWM events are generated each time a

match between the internal counter and one of the

Period registers occurs.

In Synchronous mode, the module begins performing

its compare or PWM operation as soon as its selected

clock source is enabled. Whenever an event occurs on

the selected Sync source, the module’s internal

counter is reset. In Trigger mode, the module waits for

a Sync event from another internal module to occur

before allowing the counter to run.

Free-Running mode is selected by default or any time

that the SYNCSELx bits (OCxCON2<4:0>) are set to

‘00000’. Synchronous or Trigger modes are selected

any time the SYNCSELx bits are set to any value

except ‘00000’. The OCTRIG bit (OCxCON2<7>)

selects either Synchronous or Trigger mode. Setting

this bit selects Trigger mode operation. In both modes,

the SYNCSELx bits determine the Sync/trigger source.

15.1.2

CASCADED (32-BIT) MODE

By default, each module operates independently with

its own set of 16-bit Timer and Duty Cycle registers. To

increase the range, adjacent even and odd numbered

modules can be configured to function as a single

32-bit module. (For example, Modules 1 and 2 are

paired, as are Modules 3 and 4, and so on.) The odd

numbered module (OCx) provides the Least Significant

16 bits of the 32-bit register pairs, and the even

numbered module (OCy) provides the Most Significant

16 bits. Wraparounds of the OCx registers cause an

increment of their corresponding OCy registers.

Cascaded operation is configured in hardware by setting

the OC32 bit (OCxCON2<8>) for both modules.

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 35. “Output Compare with

Dedicated Timer” (DS39723).

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