PIC24F32KA302-ISLASHML datasheet(154/364 Pages) MICROCHIP

154 / 364 page

PIC24FV32KA304 FAMILY

DS39995D-page 154

 2011-2013 Microchip Technology Inc.

15.3

Pulse-Width Modulation (PWM)

Mode

In PWM mode, the output compare module can be

configured for edge-aligned or center-aligned pulse

waveform generation. All PWM operations are

double-buffered (buffer registers are internal to the

module and are not mapped into SFR space).

To configure the output compare module for

edge-aligned PWM operation:

Calculate the desired ON time and load it into

the OCxR register.

Calculate the desired period and load it into the

OCxRS register.

Select the current OCx as the synchronization

source by writing 0x1F to SYNCSEL<4:0>

(OCxCON2<4:0>)

and

‘0’

OCTRIG

(OCxCON2<7>).

Select

clock

source

writing

the

OCTSEL2<2:0> (OCxCON<12:10>) bits.

Enable interrupts, if required, for the timer and

output compare modules. The output compare

interrupt is required for PWM Fault pin utilization.

Select the desired PWM mode in the OCM<2:0>

(OCxCON1<2:0>) bits.

If a timer is selected as a clock source, set the

TMRy prescale value and enable the time base by

setting the TON (TxCON<15>) bit.

FIGURE 15-2:

OUTPUT COMPARE x BLOCK DIAGRAM (DOUBLE-BUFFERED,

16-BIT PWM MODE)

OCxR and DCB<1:0> Buffers

Comparator

OCxTMR

OCxCON1

OCxCON2

OC Output Timing

OCx Interrupt

OCx Pin

OCxRS Buffer

Comparator

and Fault Logic

Match

Trigger and

Sync Logic

Clock

Select

Increment

Reset

OC Clock

Sources

Trigger and

Sync Sources

Reset

Match Event

OCFA/OCFB/CxOUT

OCTSELx

SYNCSELx

TRIGSTAT

TRIGMODE

OCTRIG

OCMx

OCINV

OCTRIS

FLTOUT

FLTTRIEN

FLTMD

ENFLTx

OCFLTx

OCxR and DCB<1:0>

OCxRS

Event

Rollover

Rollover/Reset

DCB<1:0>

PIC24F32KA302-I/ML Datasheet(PDF) 154 Page - Microchip Technology

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