PIC24F32KA302-ISLASHML datasheet(153/364 Pages) MICROCHIP

153 / 364 page

 2011-2013 Microchip Technology Inc.

DS39995D-page 153

PIC24FV32KA304 FAMILY

15.2

Compare Operations

In Compare mode (Figure 15-1), the output compare

module can be configured for single-shot or continuous

pulse generation. It can also repeatedly toggle an

output pin on each timer event.

To set up the module for compare operations:

Calculate the required values for the OCxR and

(for Double Compare modes) OCxRS Duty

Cycle registers:

Determine the instruction clock cycle time.

Take into account the frequency of the

external clock to the timer source (if one is

used) and the timer prescaler settings.

Calculate the time to the rising edge of the

output pulse relative to the timer start value

(0000h).

Calculate the time to the falling edge of the

pulse, based on the desired pulse width and

the time to the rising edge of the pulse.

Write the rising edge value to OCxR and the

falling edge value to OCxRS.

For Trigger mode operations, set OCTRIG to

enable Trigger mode. Set or clear TRIGMODE

configure

the

trigger

operation

and

TRIGSTAT to select a hardware or software

trigger. For Synchronous mode, clear OCTRIG.

Set the SYNCSEL<4:0> bits to configure the

trigger or synchronization source. If free-running

timer operation is required, set the SYNCSELx

bits to ‘00000’ (no Sync/trigger source).

Select

the

time

base

source

with

the

OCTSEL<2:0> bits. If the desired clock source is

running, set the OCTSEL<2:0> bits before the

output compare module is enabled for proper

synchronization with the desired clock source. If

necessary, set the TON bit for the selected timer

which enables the compare time base to count.

Synchronous mode operation starts as soon as

the synchronization source is enabled; Trigger

mode operation starts after a trigger source event

occurs.

Set the OCM<2:0> bits for the appropriate

compare operation (‘0xx’).

For 32-bit cascaded operation, these steps are also

necessary:

Set

the

OC32

bits

for

both

registers

(OCyCON2<8> and (OCxCON2<8>). Enable

the even numbered module first to ensure the

modules will start functioning in unison.

Clear the OCTRIG bit of the even module

(OCyCON2), so the module will run in

Synchronous mode.

Configure the desired output and Fault settings

for OCy.

Force the output pin for OCx to the output state

by clearing the OCTRIS bit.

If Trigger mode operation is required, configure

the trigger options in OCx by using the OCTRIG

(OCxCON2<7>), TRIGSTAT (OCxCON2<6>)

and SYNCSELx (OCxCON2<4:0>) bits.

Configure the desired Compare or PWM mode

of operation (OCM<2:0>) for OCy first, then for

OCx.

Depending on the output mode selected, the module

holds the OCx pin in its default state and forces a

transition to the opposite state when OCxR matches

the timer. In Double Compare modes, OCx is forced

back to its default state when a match with OCxRS

occurs. The OCxIF interrupt flag is set after an OCxR

match in Single Compare modes and after each

OCxRS match in Double Compare modes.

Single-shot pulse events only occur once, but may be

repeated by simply rewriting the value of the

OCxCON1 register. Continuous pulse events continue

indefinitely until terminated.

PIC24F32KA302-I/ML Datasheet(PDF) 153 Page - Microchip Technology

PIC24F32KA302-I/ML Datasheet(HTML) 153 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL