PIC24F32KA302-ISLASHML datasheet(165/364 Pages) MICROCHIP

165 / 364 page

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DS39995D-page 165

PIC24FV32KA304 FAMILY

bit 1

SPITBF: SPIx Transmit Buffer Full Status bit

1 = Transmit has not yet started, SPIxTXB is full

0 = Transmit has started, SPIxTXB is empty

In Standard Buffer mode:

Automatically set in hardware when the CPU writes the SPIxBUF location, loading SPIxTXB. Automatically

cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.

In Enhanced Buffer mode:

Automatically set in hardware when the CPU writes the SPIxBUF location, loading the last available buffer

location. Automatically cleared in hardware when a buffer location is available for a CPU write.

bit 0

SPIRBF: SPIx Receive Buffer Full Status bit

1 = Receive is complete, SPIxRXB is full

0 = Receive is not complete, SPIxRXB is empty

In Standard Buffer mode:

Automatically set in hardware when the SPIx transfers data from the SPIxSR to SPIxRXB. Automatically

cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.

In Enhanced Buffer mode:

Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread buffer

location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR.

SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)

PIC24F32KA302-I/ML Datasheet(PDF) 165 Page - Microchip Technology