PIC24F32KA302-ISLASHML datasheet(169/364 Pages) MICROCHIP

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DS39995D-page 169

PIC24FV32KA304 FAMILY

17.0 INTER-INTEGRATED

CIRCUIT™ (I2C™)

The Inter-Integrated Circuit (I2C™) module is a serial

interface

useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial data EEPROMs, display drivers,

A/D Converters, etc.

The I2C modules support these features:

• Independent master and slave logic

• 7-bit and 10-bit device addresses

• General call address, as defined in the I2C protocol

• Clock stretching to provide delays for the

processor to respond to a slave data request

• Both 100 kHz and 400 kHz bus specifications

• Configurable address masking

• Multi-Master modes to prevent loss of messages

in arbitration

• Bus Repeater mode, allowing the acceptance of

all messages as a slave, regardless of the

address

• Automatic SCL

A block diagram of the module is shown in Figure 17-1.

17.1

Pin Remapping Options

The I2C modules are tied to a fixed pin. To allow flexi-

bility with peripheral multiplexing, the I2C1 module in

28-pin devices, can be reassigned to the alternate pins.

These alternate pins are designated as SCL1 and

SDA1 during device configuration.

Pin assignment is controlled by the I2CxSEL

Configuration bit. Programming this bit (= 0) multiplexes

the module to the SCL1 and SDA1 pins.

17.2

Communicating as a Master in a

Single Master Environment

The details of sending a message in Master mode

depends on the communication protocols for the device

being communicated with. Typically, the sequence of

events is as follows:

Assert a Start condition on SDAx and SCLx.

Send the I2C device address byte to the slave

with a write indication.

Wait for and verify an Acknowledge from the

slave.

Send the first data byte (sometimes known as

the command) to the slave.

Wait for and verify an Acknowledge from the

slave.

Send the serial memory address low byte to the

slave.

Repeat Steps 4 and 5, until all data bytes are

sent.

Assert a Repeated Start condition on SDAx and

SCLx.

Send the device address byte to the slave with

a read indication.

10. Wait for and verify an Acknowledge from the

slave.

11. Enable master reception to receive serial

memory data.

12. Generate an ACK or NACK condition at the end

of a received byte of data.

13. Generate a Stop condition on SDAx and SCLx.

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information on the

Inter-Integrated Circuit, refer to the

“PIC24F Family Reference Manual”,

Section 24. “Inter-Integrated Circuit™

(I2C™)” (DS39702).

Note:

Throughout this section, references to

associated with a specific I2C module are

referred to generically by the use of ‘x’ in

place of the specific module number. Thus,

“I2CxSTAT” might refer to the Receive

Status register for either I2C1 or I2C2.

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