PIC24F32KA302-ISLASHML datasheet(171/364 Pages) MICROCHIP

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DS39995D-page 171

PIC24FV32KA304 FAMILY

17.3

Setting Baud Rate When

Operating as a Bus Master

To compute the Baud Rate Generator (BRG) reload

value, use Equation 17-1.

EQUATION 17-1:

COMPUTING BAUD RATE

RELOAD VALUE(1)

17.4

Slave Address Masking

The I2CxMSK register (Register 17-3) designates

address bit positions as “don’t care” for both 7-Bit and

10-Bit Addressing modes. Setting a particular bit

location (= 1) in the I2CxMSK register causes the slave

module to respond, whether the corresponding

address bit value is ‘0’ or ‘1’. For example, when

I2CxMSK is set to ‘00100000’, the slave module will

detect both addresses: ‘0000000’ and ‘00100000’.

To enable address masking, the Intelligent Peripheral

Management Interface (IPMI) must be disabled by

clearing the IPMIEN bit (I2C1CON<11>).

TABLE 17-1:

I2C™ CLOCK RATES(1)

TABLE 17-2:

I2C™ RESERVED ADDRESSES(1)

I2CxBRG

FCY

FSCL

------------

FCY

10 000 000



------------------------------

–



 1

–

FSCL

FCY

I2CxBRG 1

FCY

10 000 000



------------------------------

----------------------------------------------------------------------

Note 1: Based on FCY = FOSC/2; Doze mode and PLL

are disabled.

Note:

As a result of changes in the I2C protocol,

the addresses in Table 17-2 are reserved

and will not be Acknowledged in Slave

mode. This includes any address mask

settings that include any of these

addresses.

Required

System

FSCL

FCY

I2CxBRG Value

Actual

FSCL

(Decimal)

(Hexadecimal)

100 kHz

16 MHz

157

100 kHz

8 MHz

100 kHz

4 MHz

99 kHz

400 kHz

16 MHz

404 kHz

400 kHz

8 MHz

404 kHz

400kHz

4MHz

385kHz

400kHz

2MHz

385kHz

1 MHz

16 MHz

1.026 MHz

1 MHz

8 MHz

1.026 MHz

1 MHz

4 MHz

0.909 MHz

Note 1:

Based on FCY = FOSC/2; Doze mode and PLL are disabled.

Slave

Address

R/W

Bit

Description

0000 000

General Call Address(2)

0000 000

Start Byte

0000 001

CBus Address

0000 010

Reserved

0000 011

Reserved

0000 1xx

HS Mode Master Code

1111 1xx

Reserved

1111 0xx

10-Bit Slave Upper Byte(3)

Note 1: The address bits listed here will never cause an address match, independent of the address mask settings.

2: This address will be Acknowledged only if GCEN = 1.

3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.

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