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PIC24F32KA302-I/ML Datasheet(PDF) 175 Page - Microchip Technology |
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PIC24F32KA302-I/ML Datasheet(HTML) 175 Page - Microchip Technology |
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175 / 364 page ![]() 2011-2013 Microchip Technology Inc. DS39995D-page 175 PIC24FV32KA304 FAMILY bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or cleared when a Start, Repeated Start or Stop is detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when a Start, Repeated Start or Stop is detected. bit 2 R/W: Read/Write Information bit (when operating as I2C slave) 1 = Read – indicates data transfer is output from the slave 0 = Write – indicates data transfer is input to the slave Hardware is set or clear after the reception of an I2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive is complete, I2CxRCV is full 0 = Receive is not complete, I2CxRCV is empty Hardware is set when I2CxRCV is written with a received byte; hardware is clear when the software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit is in progress, I2CxTRN is full 0 = Transmit is complete, I2CxTRN is empty Hardware is set when the software writes to I2CxTRN; hardware is clear at the completion of data transmission. REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) |
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