ADAU1761BCPZ-R7 datasheet(42/92 Pages) AD

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ADAU1761

Rev. C | Page 42 of 92

SERIAL DATA INPUT/OUTPUT PORTS

The flexible serial data input and output ports of the ADAU1761

can be set to accept or transmit data in 2-channel format or in

a 4-channel or 8-channel TDM stream to interface to external

ADCs or DACs. Data is processed in twos complement, MSB

first format. The left channel data field always precedes the right

channel data field in 2-channel streams. In TDM mode, Slot 0

to Slot 3 are in the first half of the audio frame, and Slot 4 to

Slot 7 are in the second half of the frame. The serial modes and

the position of the data in the frame are set in Register R15 to

Address 0x4015 to Address 0x4018).

If the PLL of the ADAU1761 is not used, the serial data clocks

must be synchronous with the ADAU1761 master clock input.

The LRCLK and BCLK pins are used to clock both the serial

input and output ports. The ADAU1761 can be set as the master

or the slave in a system. Because there is only one set of serial

data clocks, the input and output ports must always be both

master or both slave.

Address 0x4015 and Address 0x4016) allow control of clock

polarity and data input modes. The valid data formats are I2S,

left-justified, right-justified (24-/20-/18-/16-bit), and TDM. In

all modes except for the right-justified modes, the serial port

inputs an arbitrary number of bits up to a limit of 24. Extra bits

do not cause an error, but they are truncated internally.

The serial port can operate with an arbitrary number of BCLK

transitions in each LRCLK frame. The LRCLK in TDM mode

can be input to the ADAU1761 either as a 50% duty cycle clock

or as a bit-wide pulse.

When the LRCLK is set as a pulse, a 47 pF capacitor should be

connected between the LRCLK pin and ground (see Figure 57).

This capacitor is necessary in both master and slave modes to

properly align the LRCLK signal to the serial data stream.

47pF

LRCLK

ADAU1761

BCLK

Figure 57. LRCLK Capacitor Alignment, TDM Pulse Mode

In TDM 8 mode, the ADAU1761 can be a master for fS up to

48 kHz. Table 24 lists the modes in which the serial output port

can function.

Table 24. Serial Output Port Master/Slave Mode Capabilities

2-Channel Modes (I2S, Left-

Justified, Right-Justified)

8-Channel TDM

48 kHz

Master and slave

96 kHz

Master and slave

Slave

Table 25 describes the proper configurations for standard audio

data formats.

Table 25. Data Format Configurations

Format

LRCLK Polarity (LRPOL)

LRCLK Mode

(LRMOD)

BCLK Polarity

(BPOL)

BCLK Cycles/Audio

Frame (BPF[2:0])

Data Delay from LRCLK

Edge (LRDEL[1:0])

I2S

(see Figure 58)

Frame begins on falling edge

50% duty cycle

Data changes

on falling edge

32 to 64

Delayed from LRCLK edge

by 1 BCLK

Left-Justified (see

Figure 59)

Frame begins on rising edge

50% duty cycle

Data changes

on falling edge

32 to 64

Aligned with LRCLK edge

Right-Justified

(see Figure 60)

Frame begins on rising edge

50% duty cycle

Data changes

on falling edge

32 to 64

Delayed from LRCLK edge

by 8 or 16 BCLKs

TDM with Clock

(see Figure 61)

Frame begins on falling edge

50% duty cycle

Data changes

on falling edge

64 to 256

Delayed from start of word

clock by 1 BCLK

TDM with Pulse

(see Figure 62)

Frame begins on rising edge

Pulse

Data changes

on falling edge

64 to 256

Delayed from start of word

clock by 1 BCLK

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