Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

ADAU1761BCPZ-R7 Datasheet(PDF) 85 Page - Analog Devices

Part # ADAU1761BCPZ-R7
Description  SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
PDF  92 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADAU1761BCPZ-R7 Datasheet(HTML) 85 Page - Analog Devices

Back Button ADAU1761BCPZ-R7 Datasheet HTML 81Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 82Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 83Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 84Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 85Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 86Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 87Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 88Page - Analog Devices ADAU1761BCPZ-R7 Datasheet HTML 89Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 85 / 92 page
background image
ADAU1761
Rev. C | Page 85 of 92
R63: DSP Slew Modes, 16,631 (0x40F7)
The DSP slew modes register sets the slew source for each output. The slew source can be either the DSP (digital slew) or the codec (analog
slew). When these bits are set to Logic 0, the codec provides volume slew according to the ASLEW[1:0] bits in Register R34 (playback
pop/click suppression register, Address 0x4028). When these bits are set to Logic 1, the slew is provided and defined by the DSP program,
disabling the codec volume slew.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
MOSLW
ROSLW
LOSLW
RHPSLW
LHPSLW
Table 88. DSP Slew Modes Register
Bits
Bit Name
Description
4
MOSLW
Mono output slew generation.
0 = codec (default).
1 = DSP.
3
ROSLW
Line output right slew generation.
0 = codec (default).
1 = DSP.
2
LOSLW
Line output left slew generation.
0 = codec (default).
1 = DSP.
1
RHPSLW
Headphone right slew generation.
0 = codec (default).
1 = DSP.
0
LHPSLW
Headphone left slew generation.
0 = codec (default).
1 = DSP.
R64: Serial Port Sampling Rate, 16,632 (0x40F8)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
SPSR[2:0]
Table 89. Serial Port Sampling Rate Register
Bits
Bit Name
Description
[2:0]
SPSR[2:0]
Serial port sampling rate. The serial port sampling rate is a ratio of the base sampling rate, fS. The base sampling
rate is determined by the operating frequency of the core clock. For most applications, the serial port sampling
rate should equal the converter sampling rate (set using the CONVSR[2:0] bits in Register R17) and the DSP sampling
rate (set using the DSPSR[3:0] bits in Register R57).
Setting
Sampling Rate
Base Sampling Rate (fS = 48 kHz)
000
fS
48 kHz, base (default)
001
fS/6
8 kHz
010
fS/4
12 kHz
011
fS/3
16 kHz
100
fS/2
24 kHz
101
fS/1.5
32 kHz
110
fS/0.5
96 kHz
111
Reserved



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com