ADAU1761BCPZ-R7 datasheet(63/92 Pages) AD

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ADAU1761

Rev. C | Page 63 of 92

R14: ALC Control 3, 16,404 (0x4014)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

NGTYP[1:0]

NGEN

NGTHR[4:0]

Table 48. ALC Control 3 Register

Bits

Bit Name

Description

[7:6]

NGTYP[1:0]

Noise gate type. When the input signal falls below the threshold for 250 ms, the noise gate can hold a constant

PGA gain, mute the ADC output, fade the PGA gain to the minimum gain value, or fade then mute.

Setting

Noise Gate

Hold PGA constant (default)

Mute ADC output (digital mute)

Fade to PGA minimum value (analog fade)

Fade then mute (analog fade/digital mute)

NGEN

Noise gate enable.

0 = disabled (default).

1 = enabled.

[4:0]

NGTHR[4:0]

Noise gate threshold. When the input signal falls below the threshold for 250 ms, the noise gate is activated.

A 1 LSB increase corresponds to a −1.5 dB change. See Table 93 for a complete list of the threshold settings.

Setting

Threshold

00000

−76.5 dB (default)

00001

−75 dB

…

11110

−31.5 dB

11111

−30 dB

R15: Serial Port Control 0, 16,405 (0x4015)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

SPSRS

LRMOD

BPOL

LRPOL

CHPF[1:0]

Table 49. Serial Port Control 0 Register

Bits

Bit Name

Description

SPSRS

Serial port sampling rate source.

0 = converter rate set in Register R17 (default).

1 = DSP rate set in Register R57.

LRMOD

LRCLK mode sets the LRCLK for either a 50% duty cycle or a pulse. The pulse mode should be at least 1 BCLK wide.

0 = 50% duty cycle (default).

1 = pulse mode.

BPOL

BCLK polarity sets the BCLK edge that triggers a change in audio data. This can be set for the falling or rising

edge of the BCLK.

0 = falling edge (default).

1 = rising edge.

LRPOL

LRCLK polarity sets the LRCLK edge that triggers the beginning of the left channel audio frame. This can be set

for the falling or rising edge of the LRCLK.

0 = falling edge (default).

1 = rising edge.

[2:1]

CHPF[1:0]

Channels per frame sets the number of channels per LRCLK frame.

Setting

Channels per LRCLK Frame

Stereo (default)

TDM 4

TDM 8

Reserved

Serial data port bus mode. Both LRCLK and BCLK are master of the serial port when set in master mode and are

serial port slave in slave mode.

0 = slave mode (default).

1 = master mode.

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