TSB81BA3DI datasheet(9/61 Pages) TI1

9 / 61 page

TSB81BA3D, TSB81BA3DI

IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS559E − DECEMBER 2002 − REVISED JUNE 2006

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

TYPE

NO.

I/O

DESCRIPTION

PCLK

CMOS

PHY clock. Provides a 98.304-MHz clock signal, synchronized with data transfers, to the LLC when

the PHY-link interface is operating in the 1394b mode (BMODE asserted). PCLK output provides a

49.152-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is

in legacy 1394a−2000 (BMODE input deasserted).

CMOS

Power-down input. A high on this terminal turns off all internal circuitry except the cable-active monitor

circuits, which control the CNA output. Asserting the PD input high also activates an internal pulldown

on the RESETz terminal to force a reset of the internal control logic.

PINT

CMOS

PHY Interrupt. The PHY uses this output to serially transfer status and interrupt information to the link

when PHY-link interface is in the 1394b mode. A bus holder is built into this terminal.

PLLGND

Supply

25,

−

PLL circuit ground terminals. These terminals must be tied together to the low-impedance circuit

board ground plane.

PLLVDD-CORE

Supply

29,

−

PLL 1.95-V circuit power terminals. A combination of high-frequency decoupling capacitors near each

terminal are suggested, such as paralleled 0.1

μF and 0.001 μF. An additional 1-μF capacitor is

required for voltage regulation, and the PLLVDD-CORE terminals must be separate from the

DVDD-CORE terminals. These supply terminals are separated from the DVDD-CORE, DVDD-3.3,

PLLVDD-3.3 and AVDD-3.3 terminals internal to the device to provide noise isolation.

PLLVDD-3.3

Supply

−

PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors near the

terminal are suggested, such as paralleled 0.1

μF and 0.001 μF. Lower frequency 10-μF filtering

capacitors are also recommended. This supply terminal is separated from the DVDD-CORE,

DVDD-3.3, PLLVDD-CORE, and AVDD-3.3 terminals internal to the device to provide noise isolation.

The DVDD-3.3 terminals must be tied together at a low-impedance point on the circuit board. The

PLLVDD-3.3, AVDD-3.3, and DVDD-3.3 terminals must be tied together with a low dc impedance

connection.

RESETz

CMOS

Logic reset input. Asserting this terminal low resets the internal logic. An internal pull-up resistor to

VDD is provided so only an external delay capacitor is required for proper power-up operation (see

power-up reset in the APPLICATIONS INFORMATION section). The RESETz terminal also

incorporates an internal pulldown which is activated when the PD input is asserted high. This input is

otherwise a standard logic input, and can also be driven by an open-drain type driver.

RSVD

This terminal must normally be left unconnected. When this terminal is probed, the terminal will show

a 98.304-MHz signal. If this is perceived as an EMI problem, then the terminal may be pulled to ground

through a 10-k

Ω resistor. However, this causes an increase of up to 340 μA in device current

consumption.

Bias

−

Current setting resistor terminals. These terminals are connected to a precision external resistance to

set the internal operating currents and cable driver output currents. A resistance of 6.34 k

Ω ±1% is

required to meet the IEEE Std 1394−1995 output voltage limits.

CMOS

Test control input. This input is used in the manufacturing test of the TSB81BA3D. For normal use this

terminal must be pulled low either through a 1-k

Ω resistor to GND or directly to GND.

CMOS

Test control input. This input is used in the manufacturing test of the TSB81BA3D. For normal use this

terminal must be pulled low either through a 1-k

Ω resistor to GND or directly to GND.

TESTM

CMOS

Test control input. This input is used in the manufacturing test of the TSB81BA3D. For normal use this

terminal must be pulled high through a 1-k

Ω resistor to VDD.

TESTW

CMOS

Test control input. This input is used in the manufacturing test of the TSB81BA3D. For normal use

this terminal must be pulled high through a 1-k

Ω resistor to VDD.

TPA0−

TPA0+

TPB0−

TPB0+

Cable

45,

46,

41,

I/O

Port 0 twisted-pair differential-signal terminals. Board traces from each pair of positive and

negative differential signal terminals must be kept matched and as short as possible to the

external load resistors and to the cable connector. Please request the S800 1394b layout

recommendations document from your TI representative.

TPA1−

TPA1+

TPB1−

TPB1+

Cable

I/O

Port 1 twisted-pair differential-signal terminals. Board traces from each pair of positive and

negative differential signal terminals must be kept matched and as short as possible to the

external load resistors and to the cable connector. Please request the S800 1394b layout

recommendations document from your TI representative.

TSB81BA3DI Datasheet(PDF) 9 Page - Texas Instruments

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