Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

MPC875CVR133 Datasheet(PDF) 47 Page - Freescale Semiconductor, Inc

Part # MPC875CVR133
Description  MPC875/MPC870 PowerQUICC??Hardware Specifications
PDF  84 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC875CVR133 Datasheet(HTML) 47 Page - Freescale Semiconductor, Inc

Back Button MPC875CVR133 Datasheet HTML 43Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 44Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 45Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 46Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 47Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 48Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 49Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 50Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 51Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 47 / 84 page
background image
MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4
Freescale Semiconductor
47
CPM Electrical Characteristics
13 CPM Electrical Characteristics
This section provides the AC and DC electrical specifications for the communications processor module
(CPM) of the MPC875/MPC870.
13.1
Port C Interrupt AC Electrical Specifications
Table 17 provides the timings for Port C interrupts.
Figure 41 shows the Port C interrupt detection timing.
Figure 41. Port C Interrupt Detection Timing
13.2
IDMA Controller AC Electrical Specifications
Table 18 provides the IDMA controller timings as shown in Figure 42 through Figure 45.
Table 17. Port C Interrupt Timing
Num
Characteristic
33.34 MHz
Unit
Min
Max
35
Port C interrupt pulse width low (edge-triggered mode)
55
—
ns
36
Port C interrupt minimum time between active edges
55
—
ns
Table 18. IDMA Controller Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
40
DREQ setup time to clock high
7
—
ns
41
DREQ hold time from clock high1
1 Applies to high-to-low mode (EDM = 1).
TBD
—
ns
42
SDACK assertion delay from clock high
—
12
ns
43
SDACK negation delay from clock low
—
12
ns
44
SDACK negation delay from TA low
—
20
ns
45
SDACK negation delay from clock high
—
15
ns
46
TA assertion to rising edge of the clock setup time (applies to external TA)7
—
ns
Port C
35
36
(Input)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com