Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

MPC875CVR133 Datasheet(PDF) 61 Page - Freescale Semiconductor, Inc

Part # MPC875CVR133
Description  MPC875/MPC870 PowerQUICC??Hardware Specifications
PDF  84 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC875CVR133 Datasheet(HTML) 61 Page - Freescale Semiconductor, Inc

Back Button MPC875CVR133 Datasheet HTML 57Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 58Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 59Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 60Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 61Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 62Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 63Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 64Page - Freescale Semiconductor, Inc MPC875CVR133 Datasheet HTML 65Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 61 / 84 page
background image
MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4
Freescale Semiconductor
61
CPM Electrical Characteristics
Figure 58. Ethernet Transmit Timing Diagram
13.8
SMC Transparent AC Electrical Specifications
Table 25 provides the SMC transparent timings as shown in Figure 59.
Table 25. SMC Transparent Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
150
SMCLK clock period1
1
SYNCCLK must be at least twice as fast as SMCLK.
100
—
ns
151
SMCLK width low
50
—
ns
151A
SMCLK width high
50
—
ns
152
SMCLK rise/fall time
—
15
ns
153
SMTXD active delay (from SMCLK falling edge)
10
50
ns
154
SMRXD/SMSYNC setup time
20
—
ns
155
RXD1/SMSYNC hold time
5
—
ns
TCLK3
128
TxD3
(Output)
128
TENA(RTS3)
(Input)
Notes:
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is negated before TENA or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
1.
2.
RENA(CD3)
(Input)
133
134
132
131
121
129
(Note 2)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com