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MPC875CVR133 Datasheet(PDF) 60 Page - Freescale Semiconductor, Inc |
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MPC875CVR133 Datasheet(HTML) 60 Page - Freescale Semiconductor, Inc |
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60 / 84 page ![]() MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 60 Freescale Semiconductor CPM Electrical Characteristics Figure 56. Ethernet Collision Timing Diagram Figure 57. Ethernet Receive Timing Diagram 138 CLKO1 low to SDACK asserted2 —20 ns 139 CLKO1 low to SDACK negated2 —20 ns 1 The ratios SYNCCLK/RCLK3 and SYNCCLK/TCLK3 must be greater than or equal to 2/1. 2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. Table 24. Ethernet Timing (continued) Num Characteristic All Frequencies Unit Min Max CLSN(CTS1) 120 (Input) RCLK3 121 RxD3 (Input) 121 RENA(CD3) (Input) 125 124 123 127 126 Last Bit |
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