CYUSB3035 datasheet(6/50 Pages) CYPRESS

6 / 50 page

CYUSB3035

Document Number: 001-84160 Rev. *B

Page 6 of 50

Figure 5. Carkit UART Pass-through Block Diagram

Host Processor Interface (P-Port)

A configurable interface enables FX3S to communicate with

various devices such as Sensor, FPGA, Host Processor, or a

Bridge chip. FX3S supports the following P-Port interfaces.

■ GPIF II (16-bit)

■ Slave FIFO Interface

■ 16-bit Asynchronous SRAM Interface

■ 16-bit Asynchronous address/data multiplexed (ADMux)

Interface

■ 16-bit Synchronous address/data multiplexed (ADMux)

Interface

■ Processor MMC slave Interface compatible with MMC System

specification, MMCA Technical Committee, Version 4.2 with

eMMC 4.3 and 4.4 Pass-Through boot

The following sections describe these P-Port interfaces.

GPIF II

The high-performance GPIF II interface enables functionality

similar to, but more advanced than, FX2LP's GPIF and Slave

FIFO interfaces.

The GPIF II is a programmable state machine that enables a

flexible interface that may function either as a master or slave in

industry-standard or proprietary interfaces. Both parallel and

serial interfaces may be implemented with GPIF II.

Here are a list of GPIF II features:

■ Functions as master or slave

■ Provides 256 firmware programmable states

■ Supports 8-bit and 16-bit parallel data bus

■ Enables interface frequencies up to 100 MHz

■ Supports 16 configurable control pins when a 16/8 data bus is

used. All control pins can be either input/output or bi-directional.

GPIF II state transitions are based on control input signals. The

control output signals are driven as a result of the GPIF II state

transitions. The INT# output signal can be controlled by GPIF II.

Refer to the GPIFII Designer tool. The GPIF II state machine’s

behavior is defined by a GPIF II descriptor. The GPIF II

descriptor is designed such that the required interface specifica-

tions are met. 8 kB of memory (separate from the 512 kB of

embedded SRAM) is dedicated to the GPIF II waveform where

the GPIF II descriptor is stored in a specific format.

Cypress’s GPIF II Designer Tool enables fast development of

GPIF II descriptors and includes examples for common inter-

faces.

Example implementations of GPIF II are the asynchronous slave

FIFO and synchronous slave FIFO interfaces.

Slave FIFO interface

The Slave FIFO interface signals are shown in Figure 6. This

interface allows an external processor to directly access up to

four buffers internal to FX3S. Further details of the Slave FIFO

interface are described on page 33.

Note

Access to all 32 buffers is also supported over the slave

FIFO interface. For details, contact Cypress Applications

Support.

Figure 6. Slave FIFO Interface

Asynchronous SRAM

This interface consists of standard asynchronous SRAM

interface signals as shown in Figure 7 on page 7. This interface

is used to access both the configuration registers and buffer

memory of FX3S. Both single-cycle and burst accesses are

supported by asynchronous interface signals.

The most significant address bit, A[7], determines whether the

configuration registers or buffer memory are accessed. When

the configuration registers are selected by asserting the address

bit A[7], the address bus bits A[6:0] point to a configuration

Carkit UART Pass-through

Interface on GPIF II

()

RXD(DP)

TXD(DM)

USB PHY

TXD

RXD

UART_ TXD

UART_ RXD

GPIO[48]

(UART_TX)

GPIO[49]

( UART_RX)

Carkit UART Pass-through

Interface on GPIOs

External

Processor

EZ-USB FX3S

SLCS#

A[1:0]

D[15:0]

SLRD#

SLOE#

SLWR#

PKTEND

FLAGA

FLAGB

Note: Multiple Flags may be configured.

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