CYUSB3035 datasheet(29/50 Pages) CYPRESS

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CYUSB3035

Document Number: 001-84160 Rev. *B

Page 29 of 50

Note

6. All parameters guaranteed by design and validated through characterization.

Table 11. Asynchronous ADMux Timing Parameters[6]

Parameter

Description

Min

Max

Units

Notes

ADMux Asynchronous READ Access Timing Parameters

tRC

Read cycle time (address valid to address

valid)

54.5

–

This parameter is dependent on when

the P-port processors deasserts OE#

tACC

Address valid to data valid

–

tCO

CE# assert to data valid

–

34.5

tAVOE

ADV# deassert to OE# assert

–

tOLZ

OE# assert to data LOW-Z

–

tOE

OE# assert to data valid

–

tHZ

Read cycle end to data HIGH-Z

–

22.5

ADMux Asynchronous WRITE Access Timing Parameters

tWC

Write cycle time (Address Valid to Address

Valid)

–

52.5

tAW

Address valid to write end

–

tCW

CE# assert to write end

–

tAVWE

ADV# deassert to WE# assert

–

tWP

WE# LOW pulse width

–

tWPH

WE# HIGH pulse width

–

tDS

Data valid setup to WE# deassert

–

tDH

Data valid hold from WE# deassert

–

ADMux Asynchronous Common READ/WRITE Access Timing Parameters

tAVS

Address valid setup to ADV# deassert

–

tAVH

Address valid hold from ADV# deassert

–

tVP

ADV# LOW pulse width

7.5

–

tCPH

CE# HIGH pulse width

–

tVPH

ADV# HIGH pulse width

–

tCEAV

CE# assert to ADV# assert

–

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