CYUSB3035 datasheet(7/50 Pages) CYPRESS

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CYUSB3035

Document Number: 001-84160 Rev. *B

Page 7 of 50

accessed as indicated by the P-Port DMA transfer register and

the transfer size is determined by the P-Port DMA transfer size

Application processors with a DMA controller that use address

auto-increment during DMA transfers, can override this by

connecting any higher-order address line (such as

A[15]/A[23]/A[31]) of the application processor to FX3S’s A[7].

In the asynchronous SRAM mode, when reading from a buffer

memory, FX3S supports two methods of reading out next data

from the buffer. The next data may be read out on the rising edge

of OE# or by toggling the least significant address bit A[0].

In this mode, the P-Port interface works with a 32.5-ns minimum

access cycle providing an interface data rate of up to 61.5 MB

per second.

Figure 7. Asynchronous SRAM Interface

Asynchronous Address/Data Multiplexed

The physical ADMux memory interface consists of signals shown

in Figure 8. This interface supports processors that implement a

multiplexed address/data bus.

Figure 8. ADMux Memory Interface

FX3S’s ADMux interface supports a 16-bit time-multiplexed

address/data SRAM bus.

For read operations, assert both CE# and OE#.

For write operations, assert both CE# and WE#. OE# is "Don't

Care" during a write operation (during both address and data

phase of the write cycle). The input data is latched on the rising

edge of WE# or CE#, whichever occurs first. Latch the addresses

prior to the write operation by toggling Address Valid (ADV#).

Assert Address Valid (ADV#) during the address phase of the

write operation, as shown in Figure 19 on page 28.

ADV# must be LOW during the address phase of a read/write

operation. ADV# must be HIGH during the data phase of a

read/write operation, as shown in Figure 18 and Figure 19 on

page 28.

Synchronous ADMux Interface

FX3S's P-Port supports a synchronous address/data

multiplexed interface. This operates at an interface frequency of

up to 100 MHz and supports a 16-bit data bus.

The RDY output signal from the FX3S device indicates a data

valid for read transfers and is acknowledged for write transfers.

Figure 9. Synchronous ADMux Interface

See the Synchronous ADMux Interface timing diagrams for

details.

Processor MMC (PMMC) Slave Interface

FX3S supports an MMC slave interface on the P-Port. This

interface is named "PMMC" to distinguish it from the S-Port MMC

interface.

Figure 10 illustrates the signals used to connect to the host

processor.

The PMMC interface's GO_IRQ_STATE command allows FX3S

to communicate asynchronous events without requiring the INT#

signal. The use of the INT# signal is optional.

Figure 10. PMMC Interface Configuration

HOST

PROCESSOR

WEST BRIDGE

BENICIA

CE#

A[7:0]

DQ[15:0]

WE#

OE#

FX3S

HOST

PROCESSOR

WEST BRIDGE

BENICIA

CE#

ADV#

A[7:0]/DQ[15:0]

WE#

OE#

FX3S

HOST

Processor

West Bridge

Benicia

CLK

CE#

ADV#

A[0:7]/DQ[0:15]

WE#

OE#

RDY

FX3S

HOST

PROCESSOR

WEST BRIDGE

BENICIA

CLK

CMD

DAT[7:0]

INT#

FX3S

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