LM4308 datasheet(19/33 Pages) TI

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LM4308

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SNLS225C – AUGUST 2007 – REVISED MAY 2013

There are also three options for the Slave to enter the sleep state. These are: based on the MPL-2 interface, the

Slave PD* input pin, and by powering off the Slave device.

With power ON, and the Slave PD* input = H, the Slave detects the state on the MPL-2 bus and powers up or

enters sleep mode. Direct control of the Slave is also possible by the use of its PD* input pin (relative to the

Slave’s VDDIO levels). The third option is to turn off power to the Slave. In this configuration, do not enable and

activate the Master outputs without the Slave also being ON.

SLAVE OUTPUT DRIVE STRENGTH CONTROL

The Slave Outputs have two drive strength options to support a wide range of VDDIO operation. See Table 2. If

the SLV VDDIO is 1.8V TYP, RDS0 and RDS1 should be set to a logic High. Depending upon application speed,

RDS0 can be set to a logic Low to soften the edge rate on the Data signals for less noise. For high VDDIO

operation (i.e. 2.8V), both RDS0 and RDS1 should be set to a logic Low.

SLAVE WRITE ONLY MODE

In some applications, only WRITE operations may be required. In this case, the Slave can be configured to only

support WRITE transactions by setting the WO configuration input High.

Application Information

SYSTEM CONSIDERATIONS

DUAL SMART DISPLAY APPLICATION

A Dual Smart Display application is shown in Figure 17. The Master (MST) resides by the host and connects to a

Memory Interface. VDDIO on the MST is set to be the same as the Host’s port. i80 CPU Bus signals are

connected as shown (Data, AD, WR*, RD*, and CS* signals). The Master also has a SLEEP mode to save

power when the display is not required. The Sleep state is entered when the PD* signal is driven Low. It is also

entered if the PD* signal is High and the CLK input is gated off (held at a static state). In the Sleep state, supply

current into the Master is >1µA typical. In this state, (Power ON, and Sleep state), the Master inputs will not load

the shared bus, and communication between the host and other devices may occur. If power is OFF (VDDIO =

0V), Master input ESD diodes will clamp the bus, preventing communication on the bus. The Master requires a

system clock reference which is typically 19.2MHz in CDMA applications. This signal is used to generate the

serial DC clock. The CLK input is multiplied by the selected PLL multiplier to determine the serial clock rate. In

the 19.2MHz CLK and 8X application, the DC rate will be 153.6MHz. Due to the serial transmission scheme

using both clock edges, the raw bandwidth of a WRITE is 307.3 Mbps. The Master also provides a ERR pin that

reports a CRC error on a READ transaction. The host may monitor this signal if desired, or it may be brought out

to a test point only. Several configuration pins are also required to be set. For a Master, tie M/S* = H, TM = L,

and PLLCON[1:0] to the desired setting.

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