EP3SE110 datasheet(45/341 Pages) ALTERA

45 / 341 page

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics

1–35

I/O Timing

Altera Corporation

Stratix III Device Handbook, Volume 2

1.5-V Differential

HSTL CLASS II

—

1.375

2.325

1.02

0.75

0.6875

1.2-V Differential

HSTL CLASS I

—

1.09

2.325

1.02

0.60

0.545

1.2-V Differential

HSTL CLASS II

—

1.09

2.325

1.02

0.60

0.545

LVDS

—

100

—

2.325

1.02

—

1.1625

MINI-LVDS

—

100

—

2.325

1.02

—

1.1625

RSDS

—

100

—

2.325

1.02

—

1.1625

LVDS_E_1R

—

100

—

120

2.325

1.02

—

1.1625

LVDS_E_3R

120

100

—

170

2.325

1.02

—

1.1625

Table 1–37. Output Timing Measurement Methodology for Output Pins (Part 2 of 3)

I/O Standard

Loading and Termination

Measurement

Point

CCIO

CCPD

L (pF)

MEAS (v)

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