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EP3SE110 Datasheet(PDF) 37 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 37 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–27
Switching Characteristics
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
Table 1–29. Transmitter Channel-to-Channel Skew (TCCS)—Write Side (Note 1) (Part 1 of 2)
Memory Type
I/O
Standard
Width
C2
C3, I3
C4, I4
C4L, I4L
C4L, I4L
V
CCL = 1.1 V
V
CCL = 1.1 V
V
CCL = 1.1 V
VCCL = 1.1 V
VCCL = 0.9 V
TCCS (ps)
TCCS (ps)
TCCS (ps)
TCCS (ps)
TCCS (ps)
Lead
Lag
Lead
Lag
Lead
Lag
Lead
Lag
Lead
Lag
DDR3 SDRAM (with
Deskew circuitry,
401 MHz–533 MHz)
1.5-V
SSTL
×4, ×8
253
262
————————
DDR3 SDRAM (8-tap
phase offset,
375 MHz–400 MHz)
1.5-V
SSTL
×4, ×8
293
284
341
332
——————
DDR3 SDRAM (8-tap
phase offset,
360 MHz–375 MHz)
1.5-V
SSTL
×4, ×8
293
284
341
373
——————
DDR3 SDRAM (10-tap
phase offset,
333 MHz–360 MHz)
1.5-V
SSTL
×4, ×8
169
470
217
496
258
528
258
528
—
—
DDR3 SDRAM (10-tap
phase offset,
300 MHz–333 MHz)
1.5-V
SSTL
×4, ×8
169
470
217
496
258
528
258
528
—
—
DDR3 SDRAM
(Non-leveling interface)
1.5-V
SSTL
×4, ×8
268
246
230
355
250
388
250
388
250
388
DDR2 SDRAM Differential
DQS
1.8-V
SSTL
×4, ×8
229
246
230
355
250
388
250
388
350
488
DDR2 SDRAM
Single-ended DQS
1.8-V
SSTL
×4, ×8
316
168
318
239
346
260
346
260
446
360
DDR SDRAM
Single-ended DQS
2.5-V
SSTL
×4, ×8
313
157
315
222
343
242
343
242
443
342
QDRII/II+ SRAM
1.5-V
HSTL
×9, ×18,
×36
290
278
292
388
315
421
315
421
415
521
QDRII/II+ SRAM
Emulation (2)
1.5-V
HSTL
×36
310
298
312
408
335
441
335
441
435
541



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