EP3SE110 datasheet(41/341 Pages) ALTERA

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics

1–31

I/O Timing

Altera Corporation

Stratix III Device Handbook, Volume 2

Preliminary and Final Timing

Timing models can have either preliminary or final status. The Quartus II software

issues an informational message during design compilation if the timing models are

preliminary. Table 1–36 lists the status of the Stratix III device timing models.

Preliminary status means that the timing models are subject to change in future

Quartus II releases. Initially, timing numbers are created using simulation results,

process data, and other known parameters. Parts of the timing models may be

correlated to silicon measurements. Various tests are used to make the preliminary

numbers as close to the actual timing parameters as possible.

Final timing models are based on simulation models that are characterized versus the

actual device measurements under all allowable operating conditions. When the

timing models are final, all or most of the Stratix III family devices have been

completely characterized and no further changes to the timing model are expected.

I/O Timing Measurement Methodology

Altera characterizes timing delays at the worst-case process, minimum voltage, and

maximum temperature for input register setup time (tsu) and hold time (th). The

Quartus II software uses the following equations to calculate tsu and th timing for the

Stratix III devices input signals.

tsu =

+ data delay from the input pin to the input register

+ micro setup time of the input register

- clock delay from the input pin to the input register

th =

- data delay from the input pin to the input register

+ micro hold time of the input register

+ clock delay from the input pin to the input register

Table 1–36. Timing Model Status for Stratix III Devices

Device

Preliminary

Final

EP3SL50

—

EP3SL70

—

EP3SL110

—

EP3SL150

—

EP3SL200

—

EP3SL340

—

EP3SE50

—

EP3SE80

—

EP3SE110

—

EP3SE260

—

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