ADSP-21062LABZ-160 datasheet(47/64 Pages) AD

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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. F

Page 47 of 64

March 2008

TEST CONDITIONS

For the ac signal specifications (timing parameters), see Timing

Specifications on Page 21. These specifications include output

disable time, output enable time, and capacitive loading. The

timing specifications for the DSP apply for the voltage reference

levels in Figure 28.

Output Disable Time

Output pins are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from their

output high or low voltage. The time for the voltage on the bus

to decay by

'V is dependent on the capacitive load, C

L, and the

load current, IL. This decay time can be approximated by the fol-

lowing equation:

The output disable time tDIS is the difference between

tMEASURED and tDECAY as shown in Figure 29. The time tMEASURED is

the interval from when the reference signal switches to when the

output voltage decays

'V from the measured output high or

output low voltage. tDECAY is calculated with test loads CL and IL,

and with

'V equal to 0.5 V.

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high impedance state to when they start driv-

ing. The output enable time tENA is the interval from when a

reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram (Figure 29). If multiple

pins (such as the data bus) are enabled, the measurement value

is that of the first pin to start driving.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate tDECAY using the equation given above. Choose

to be the difference between the ADSP-2106x’s output voltage

and the input threshold for the device requiring the hold time. A

typical

'V will be 0.4 V. C

L is the total bus capacitance (per data

line), and IL is the total leakage or three-state current (per data

line). The hold time will be tDECAY plus the minimum disable

time (i.e., tDATRWH for the write cycle).

Capacitive Loading

Output delays and holds are based on standard capacitive loads:

50 pF on all pins (see Figure 30). The delay and hold specifica-

tions given should be derated by a factor of 1.5 ns/50 pF for

loads other than the nominal value of 50 pF. Figure 32,

Figure 33, Figure 37, and Figure 38 show how output rise time

varies with capacitance. Figure 34 and Figure 36 show

graphically how output delays and holds vary with load capaci-

tance. (Note that this graph or derating does not apply to output

disable delays; see the previous section Output Disable Time

under Test Conditions.) The graphs of Figure 32, Figure 33,

Figure 37, and Figure 38 may not be linear outside the ranges

shown.

Output Drive Characteristics

Figure 31 shows typical I-V characteristics for the output driv-

ers of the ADSP-2106x. The curves represent the current drive

capability of the output drivers as a function of output voltage.

Figure 28. Voltage Reference Levels for AC Measurements (Except Output

Enable/Disable)

Figure 29. Output Enable/Disable

INPUT

OUTPUT

1.5V

PEXT

CL V

--------------

REFERENCE

SIGNAL

tDIS

OUTPUT STARTS

DRIVING

VOH (MEASURED) - V

VOL (MEASURED) + V

tMEASURED

VOH (MEASURED)

VOL (MEASURED)

2.0V

1.0V

VOH (MEASURED)

VOL (MEASURED)

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE

THIS VOLTAGE TO BE

APPROXIMATELY 1.5V

OUTPUT STOPS

DRIVING

tENA

tDECAY

Figure 30. Equivalent Device Loading for AC Measurements (Includes All

Fixtures)

+1.5V

50pF

OUTPUT

IOL

IOH

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