ADSP-21062LABZ-160 datasheet(22/64 Pages) AD

22 / 64 page

Rev. F

Page 22 of 64

March 2008

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Clock Input

Reset

Table 9. Clock Input

Parameter

ADSP-21060

ADSP-21062

40 MHz, 5 V

ADSP-21060

ADSP-21062

33 MHz, 5 V

ADSP-21060L

ADSP-21062L

40 MHz, 3.3 V

ADSP-21060L

ADSP-21062L

33 MHz, 3.3 V

Unit

MinMax

Min

Max

MinMax

Timing Requirements

tCK

CLKIN Period

100

tCKL

CLKIN Width Low

8.75

8.751

tCKH

CLKIN Width High

55ns

tCKRF

CLKIN Rise/Fall (0.4 V to 2.0 V)

1 For the ADSP-21060LC, this specification is 9.5 ns min.

Figure 9. Clock Input

CLKIN

tCKH

tCKL

tCK

Table 10. Reset

5 V and 3.3 V

Unit

Parameter

Min

Max

Timing Requirements

tWRST

RESET Pulse Width Low1

4tCK

tSRST

RESET Setup Before CLKIN High2

14 + DT/2

tCK

1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable

VDD and CLKIN (not including start-up time of external clock oscillator).

2 Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-2106xs commu-

nicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.

Figure 10. Reset

CLKIN

RESET

tWRST

tSRST

ADSP-21062LABZ-160 Datasheet(PDF) 22 Page - Analog Devices

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