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DSPIC33FJ32GP302TH/SP Datasheet(PDF) 259 Page - Microchip Technology |
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DSPIC33FJ32GP302TH/SP Datasheet(HTML) 259 Page - Microchip Technology |
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259 / 403 page  2009 Microchip Technology Inc. Preliminary DS70292D-page 259 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 21-2: AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 VCFG<2:0> — — CSCNA CHPS<1:0> bit 15 bit 8 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS — SMPI<3:0> BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits bit 12-11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Scan Input Selections for CH0+ during Sample A bit 1 = Scan inputs 0 = Do not scan inputs bit 9-8 CHPS<1:0>: Selects Channels Utilized bits When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’ 1x = Converts CH0, CH1, CH2 and CH3 01 = Converts CH0 and CH1 00 = Converts CH0 bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1) 1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7 0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF bit 6 Unimplemented: Read as ‘0’ bit 5-2 SMPI<3:0>: Selects Increment Rate for DMA Addresses bits or number of sample/conversion operations per interrupt 1111 = Increments the DMA address or generates interrupt after completion of every 16th sample/ conversion operation 1110 = Increments the DMA address or generates interrupt after completion of every 15th sample/ conversion operation • • • 0001 = Increments the DMA address after completion of every 2nd sample/conversion operation 0000 = Increments the DMA address after completion of every sample/conversion operation bit 1 BUFM: Buffer Fill Mode Select bit 1 = Starts buffer filling at address 0x0 on first interrupt and 0x8 on next interrupt 0 = Always starts filling buffer at address 0x0 bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A ADREF+ ADREF- 000 AVDD AVSS 001 External VREF+AVSS 010 AVDD External VREF- 011 External VREF+ External VREF- 1xx AVDD Avss |
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