DSPIC33FJ32GP302THSLASHSP datasheet(388/403 Pages) MICROCHIP

388 / 403 page

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

DS70292D-page 388

Preliminary

 2009 Microchip Technology Inc.

Revision C (May 2009)

This

revision

includes

minor

typographical

and

formatting changes throughout the data sheet text.

Global changes include:

• Changed all instances of OSCI to OSC1 and

OSCO to OSC2

• Changed all instances of VDDCORE and VDDCORE/

VCAP to VCAP/VDDCORE

The other changes are referenced by their respective

section in the following table.

TABLE A-2:

MAJOR SECTION UPDATES

Section Name

Update Description

High-Performance, 16-Bit Digital

Signal Controllers

Updated all pin diagrams to denote the pin voltage tolerance (see “Pin

Diagrams”).

Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which

references pin connections to VSS.

Section 1.0 “Device Overview”

Updated AVDD in the PINOUT I/O Descriptions (see Table 1-1).

Added Peripheral Pin Select (PPS) capability column to Pinout I/O

Descriptions (see Table 1-1).

Section 2.0 “Guidelines for Getting

Started with 16-Bit Digital Signal

Controllers”

Added new section to the data sheet that provides guidelines on getting

started with 16-bit Digital Signal Controllers.

Section 3.0 “CPU”

Updated CPU Core Block Diagram with a connection from the DSP Engine

to the Y Data Bus (see Figure 3-1).

Vertically extended the X and Y Data Bus lines in the DSP Engine Block

Diagram (see Figure 3-3).

Section 4.0 “Memory Organization”

Updated Reset value for CORCON in the CPU Core Register Map (see

Table 4-1).

Updated the Reset values for IPC14 and IPC15 and removed the FLTA1IE

bit (IEC3) from the Interrupt Controller Register Map (see Table 4-4).

Updated bit locations for RPINR25 in the Peripheral Pin Select Input

Updated the Reset value for CLKDIV in the System Control Register Map

(see Table 4-33).

Section 5.0 “Flash Program

Memory”

Updated Section 5.3 “Programming Operations” with programming time

formula.

Section 9.0 “Oscillator

Configuration”

Updated the Oscillator System Diagram and added Note 2 (see Figure 9-1).

Added Note 1 and Note 2 to the OSCON register (see Register 9-1).

Updated default bit values for DOZE<2:0> and FRCDIV<2:0> in the Clock

Divisor (CLKDIV) Register (see Register 9-2).

Added a paragraph regarding FRC accuracy at the end of Section 9.1.1

“System Clock Sources”.

Added Note 3 to Section 9.2.2 “Oscillator Switching Sequence”.

Added Note 1 to the FRC Oscillator Tuning (OSCTUN) Register (see

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