DSPIC33FJ32GP302THSLASHSP datasheet(389/403 Pages) MICROCHIP

389 / 403 page

 2009 Microchip Technology Inc.

Preliminary

DS70292D-page 389

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

Section 10.0 “Power-Saving

Features”

Added the following registers:

• PMD1: Peripheral Module Disable Control Register 1 (Register 10-1)

• PMD2: Peripheral Module Disable Control Register 2 (Register 10-2)

• PMD3: Peripheral Module Disable Control Register 3 (Register 10-3)

Section 11.0 “I/O Ports”

Removed Table 11-1 and added reference to pin diagrams for I/O pin

availability and functionality.

Added paragraph on ADPCFG register default values to Section 11.3

“Configuring Analog Port Pins”.

Added Note box regarding PPS functionality with input mapping to

Section 11.6.2.1 “Input Mapping”.

Section 16.0 “Serial Peripheral

Interface (SPI)”

Added Note 2 and 3 to the SPIxCON1 register (see Register 16-2).

Section 18.0 “Universal

Asynchronous Receiver Transmitter

(UART)”

Updated the Notes in the UxMode register (see Register 18-1).

Updated the UTXINV bit settings in the UxSTA register and added Note 1

(see Register 18-2).

Section 19.0 “Enhanced CAN

(ECAN™) Module”

Changed bit 11 in the ECAN Control Register 1 (CiCTRL1) to Reserved (see

Section 21.0 “10-Bit/12-Bit Analog-

to-Digital Converter (ADC)”

Replaced the ADC1 Module Block Diagrams with new diagrams (see

Figure 21-1 and Figure 21-2).

Updated bit values for ADCS<7:0> and added Notes 1 and 2 to the ADC1

Control Register 3 (AD1CON3) (see Register 21-3).

Added Note 2 to the ADC1 Input Scan Select Register Low (AD1CSSL) (see

Added Note 2 to the ADC1 Port Configuration Register Low (AD1PCFGL)

(see Register 21-8).

Section 22.0 “Audio Digital-to-

Analog Converter (DAC)”

Updated the midpoint voltage in the last sentence of the first paragraph.

Updated the voltage swing values in the last sentence of the last paragraph

in Section 22.3 “DAC Output Format”.

Section 23.0 “Comparator Module”

Updated the Comparator Voltage Reference Block Diagram

(see Figure 23-2).

Section 24.0 “Real-Time Clock and

Calendar (RTCC)”

Updated the minimum positive adjust value for CAL<7:0> in the RTCC

Calibration and Configuration (RCFGCAL) Register (see Register 24-1).

Section 27.0 “Special Features”

Added Note 1 to the Device Configuration Register Map (see Table 27-1).

Updated Note 1 in the dsPIC33F Configuration Bits Description (see

Table 27-2).

TABLE A-2:

MAJOR SECTION UPDATES (CONTINUED)

Section Name

Update Description

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