MPC8245EC datasheet(24/68 Pages) FREESCALE

24 / 68 page

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 14 provides the AC test load for the MPC8245.

Figure 14. AC Test Load for the MPC8245

14b

sys_logic_clk to output high impedance (for all others)

—

4.0

Notes:

1. All PCI signals are measured from GVDD/2 of the rising edge of PCI_SYNC_IN to 0.285 × OVDD or 0.615 × OVDD of the

signal in question for 3.3 V PCI signaling levels. See Figure 12.

2. All memory and related interface output signal specifications are specified from the VM = 1.4 V of the rising edge of the

memory bus clock, sys_logic_clk to the TTL level (0.8 or 2.0 V) of the signal in question. sys_logic_clk is the same as

PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every

rising and falling edge of PCI_SYNC_IN). See Figure 11.

3. PCI bused signals are composed of the following signals: LOCK, IRDY, C/BE[3:0], PAR, TRDY, FRAME, STOP, DEVSEL,

PERR, SERR, AD[31:0], REQ[4:0], GNT[4:0], IDSEL, and INTA.

4. To meet minimum output hold specifications relative to PCI_SYNC_IN for both 33- and 66-MHz PCI systems, the MPC8245

has a programmable output hold delay for PCI signals (the PCI_SYNC_IN to output valid timing is also affected). The initial

value of the output hold delay is determined by the values on the MCP and CKE reset configuration signals; the values on

these two signals are inverted and stored as the initial settings of PCI_HOLD_DEL = PMCR2[5, 4] (power management

configuration register 2 <0x72>), respectively. Since MCP and CKE have internal pull-up resistors, the default value of

PCI_HOLD_DEL after reset is 0b00. Further output hold delay values are available by programming the PCI_HOLD_DEL

value of the PMCR2 configuration register. Figure 15 shows the PCI_HOLD_DEL effect on output valid and hold times.

Table 11. Output AC Timing Specifications (continued)

Num

Characteristic

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

OVDD/2 for PCI

RL = 50 Ω

Output Measurements are Made at the Device Pin

GVDD/2 for Memory

MPC8245EC Datasheet(PDF) 24 Page - Freescale Semiconductor, Inc